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PDF AAT4282A Data sheet ( Hoja de datos )
| Número de pieza | AAT4282A | |
| Descripción | Dual Slew Rate Controlled Load Switch | |
| Fabricantes | Advanced Analogic Technologies | |
| Logotipo |  |
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AAT4282A
Dual Slew Rate Controlled Load Switch
General Description
Features
SmartSwitch™
The AAT4282A SmartSwitch™ is a member of
AnalogicTech's Application Specific Power MOS-
FET™ (ASPM™) product family. The AAT4282A is
a dual P-channel MOSFET power switch designed
for high-side load-switching applications. Each
MOSFET has a typical RDS(ON) of 60mΩ, allowing
increased load switch current handling capacity with
a low forward voltage drop. The device is available
in three different versions with flexible turn-on and
turn-off characteristics – from very fast to slew-rate
limited. The standard 4282A (-1) version has a slew-
rate limited turn-on load switch. The AAT4282A (-2)
version features fast turn-on capability, typically less
than 500ns turn-on and 3µs turn-off times. The
AAT4282A (-3) variation offers a shutdown load dis-
charge circuit to rapidly turn off a load circuit when
the switch is disabled. An additional feature is a
slew-rate selector pin which can switch between fast
and slow slew rate.
All the AAT4282A load switch versions are
designed to operate from 1.5V up to 6.5V, making
them ideal for both 3V and 5V systems. Input logic
levels are TTL and 2.5V to 5V CMOS compatible.
The quiescent supply current is a very low 1µA.
The AAT4282A is available in the Pb-free, low pro-
file 2.0x2.0mm FTDFN22-8 package and is speci-
fied over the -40 to 85°C temperature range.
• VIN Range: 1.5V to 6.5V
• Low RDS(ON)
— 60mΩ Typical @ 5V
— 140mΩ Typical @ 1.5V
• Slew Rate Turn-On Time Options
— 1ms
— 0.5µs
— 100µs
• Fast Shutdown Load Discharge Option
• Low Quiescent Current
— Typically 1µA
• TTL/CMOS Input Logic Level
• Temperature Range -40ºC to 85°C
• FTDFN22-8 Package
Applications
www.DataSheet.net/
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Cellular Telephones
Digital Still Cameras
Hotswap Supplies
Notebook Computers
PDA Phones
PDAs
PMPs
Smartphones
Typical Application
INA
INB
C1
1μF
INA OUTA
ON/OFF
INB OUTB
ENA AAT4282A
C2
1μF
ON/OFF
FAST/ SLOW
ENB
FAST
GND
N/C
OUTA
OUTB
C3
0.1μF
C4
0.1μF
4282A.2007.09.1.1
1
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
AAT4282A
Dual Slew Rate Controlled Load Switch
Typical Characteristics
VIN = 5V, TA = 25ºC unless otherwise noted.
Quiescent Current vs. Temperature
(No Load; Single Switch)
12
10
8 VIN = 5V
6
4
2 VIN = 3V
0
-40 -15 10 35 60
Temperature (°C)
85
Quiescent Current vs. Input Voltage
(No Load; Single Switch)
12
10
8
6
4
2
0
01 23 4 5 6
Input Voltage (V)
Off Supply Current vs. Temperature
(No Load; EN = GND; VIN = 5V)
Typical ON/OFF Threshold vs. Input Voltage
1 1.3
0.9
0.8
0.7
0.6
www.DataSheet.net/
1.2
1.1
1
VIH
0.5
0.4
0.9 VIL
0.3 0.8
0.2
0.7
0.1
0
-40 -15 10 35 60 85
0.6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Temperature (°C)
Input Voltage (V)
On-Resistance vs. Temperature
100
90
80
70
60
50
40
30
20
10
0
-40
VIN = 3V
VIN = 5V
-15 10 35 60
Temperature (°C)
85
On-Resistance vs. Input Voltage
220
200
180
160
ISW = 2A
140
120
100
80
60 ISW = 100mA
40
1.5
2.5
3.5 4.5
Input Voltage (V)
5.5
6.5
4282A.2007.09.1.1
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
AAT4282A
Dual Slew Rate Controlled Load Switch
High Peak Output Current Applications
Some applications require the load switch to oper-
ate at a continuous nominal current level with short
duration, high-current peaks. Refer to the IDM spec-
ification in the Absolute Maximum Ratings table to
ensure the AAT4282A’s maximum pulsed current
rating is not exceeded. The duty cycle for both out-
put current levels must be taken into account. To do
so, first calculate the power dissipation at the nom-
inal continuous current level, and then add the
additional power dissipation due to the short dura-
tion, high-current peak scaled by the duty factor.
For example, a 4V system using an AAT4282A
which has channel A operates at a continuous 1A
load current level, and channel B operates at a
continuous 100mA load current level and has short
3A current peaks, as in a GSM application. The
current peak occurs for 576μs out of a 4.61ms peri-
od. First, the current duty cycle is calculated:
⎛ x ⎞ ⎛ 576μs ⎞
% Peak Duty Cycle = ⎝ 100⎠ = ⎝ 4.61ms⎠
% Peak Duty Cycle = 12.5%
The load current is 100mA for 87.5% of the 4.61ms
period and 3A for 12.5% of the period. Since the
Electrical Characteristics do not report RDS(MAX) for
4V operation, it must be approximated by consult-
ing the chart of RDS(ON) vs. VIN. The RDS reported
for 5V at 100mA and 3A can be scaled by the ratio
seen in the chart to derive the RDS for 4V VIN at
25°C: 130mΩ · 63mΩ /60mΩ = 136.5mΩ . De-
rated for temperature: 136.5mΩ · (1 + 0.002800 ·
(125°C - 25°C)) = 174.7mΩ.
For channel A, the power dissipation for a continu-
ous 1A load is calculated as follows:
PD(CHA) = IOUT2 · RDS = (1A)2 · 174.7mΩ = 174.7mW
For channel B, the power dissipation for 100mA
load is calculated as follows:
PD(MAX) = IOUT2 · RDS
PD(100mA) = (100mA)2 · 174.7mΩ
PD(100mA) = 1.75mW
PD(87.5%D/C) = %DC · PD(100mA)
PD(87.5%D/C) = 0.875 · 1.75mW
PD(87.5%D/C) = 1.53mW
The power dissipation for 100mA load at 87.5%
duty cycle is 1.53mW. Now the power dissipation
for the remaining 12.5% of the duty cycle at 3A is
calculated:
PD(MAX) = IOUT2 · RDS
PD(3A) = (3A)2 · 174.7mΩ
PD(3A) = 1572mW
PD(12.5%D/C) = %DC · PD(3A)
PD(12.5%D/C) = 0.125 · 1572mW
PD(12.5%D/C) = 196.7mW
Finally, the total power dissipation for channels A
and B is determined as follows:
PD(total) = PD(CHA) + PD(100mA) + PD(3A)
PD(total) = 174.7mW + 1.53mW + 196.7mW
PD(total) = 373mW
The maximum power dissipation for the AAT4282A
operating at an ambient temperature of 85°C is
373mW. The device in this example will have a
w w w . totalD a t a S h powere e t . n e t / dissipation of 571mW. This is well with-
in the thermal limits for safe operation of the
device; in fact, at 85°C, the AAT4282A will handle
a 3A pulse for up to 25% duty cycle. At lower ambi-
ent temperatures, the duty cycle can be further
increased.
Printed Circuit Board Layout
Recommendations
For proper thermal management, and to take
advantage of the low RDS(ON) of the AAT4282A, a
few circuit board layout rules should be followed:
VIN and VOUT should be routed using wider than
normal traces, and GND should be connected to a
ground plane. For best performance, CIN and COUT
should be placed close to the package pins.
4282A.2007.09.1.1
11
Datasheet
11 Page | ||
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