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PDF LPC1788 Data sheet ( Hoja de datos )
| Número de pieza | LPC1788 | |
| Descripción | (LPC177x / LPC178x) 32-bit ARM Cortex-M3 microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC178x/7x
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC
Rev. 4.1 — 15 November 2012
Product data sheet
1. General description
The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation.
The Cortex-M3 is a next generation core that offers better performance than the ARM7 at
the same clock rate and other system enhancements such as modernized debug features
and a higher level of support block integration. The Cortex-M3 CPU incorporates a
3-stage pipeline and has a Harvard architecture with separate local instruction and data
buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branches.
The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC178x/7x operates at up to
120 MHz CPU frequency.
The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,
External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB
Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,
three
I2C-bus
interfaces,
one
www.DataSheet.net/
eight-channel,
12-bit
ADC,
a
10-bit
DAC,
a
Quadrature
Encoder Interface, four general purpose timers, two general purpose PWMs with six
outputs each and one motor control PWM, an ultra-low power RTC with separate battery
supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to
165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allow
pin function compatibility with the LPC24xx and LPC23xx.
2. Features and benefits
Functional replacement for the LPC23xx and LPC24xx family devices.
System:
ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU,USB, Ethernet, and the General Purpose DMA
controller. This interconnect provides communication with no arbitration delays
unless two masters attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC1788
LPC1788FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
LPC1788FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
LPC1788FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC1787
LPC1787FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1786
LPC1786FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1785
LPC1785FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1778
LPC1778FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1778FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
LPC1778FET180
LPC1778FBD144
TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
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LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC1777
LPC1777FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1776
LPC1776FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1776FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
LPC1774
LPC1774FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC1774FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
Version
SOT459-1
SOT950-1
SOT570-2
SOT486-1
SOT459-1
SOT459-1
SOT459-1
SOT459-1
SOT950-1
SOT570-2
SOT486-1
SOT459-1
SOT459-1
SOT570-2
SOT459-1
SOT486-1
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.1 — 15 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 120
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Description
P0[5]
P0[6]
P0[7]
166 C12 B11 115 [3] I; I/O
PU I/O
O
I
-
-
-
O
164 D13 D11 113 [3] I; I/O
PU I/O
I/O
O
O
162 C13 B12 112 [4]
-
-
O
I; IA I/O
I/O
I/O
O
I
-
-
O
P0[5] — General purpose digital input/output pin.
I2S_RX_WS — I2S Receive word select. It is driven by the
master and received by the slave. Corresponds to the signal WS
in the I2S-bus specification.
CAN_TD2 — CAN2 transmitter output.
T2_CAP1 — Capture input for Timer 2, channel 1.
R — Function reserved.
R — Function reserved.
R — Function reserved.
LCD_VD[1] — LCD data.
P0[6] — General purpose digital input/output pin.
I2S_RX_SDA — I2S Receive data. It is driven by the transmitter
and read by the receiver. Corresponds to the signal SD in the
I2S-bus specification.
SSP1_SSEL — Slave Select for SSP1.
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T2_MAT0 — Match output for Timer 2, channel 0.
U1_RTS — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART1.
R — Function reserved.
R — Function reserved.
LCD_VD[8] — LCD data.
P0[7] — General purpose digital input/output pin.
I2S_TX_SCK — I2S transmit clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in the
I2S-bus specification.
SSP1_SCK — Serial Clock for SSP1.
T2_MAT1 — Match output for Timer 2, channel 1.
RTC_EV0 — Event input 0 to Event Monitor/Recorder.
R — Function reserved.
R — Function reserved.
LCD_VD[9] — LCD data.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.1 — 15 November 2012
© NXP B.V. 2012. All rights reserved.
11 of 120
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC1788.PDF ] | |
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