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PDF LPC1104 Data sheet ( Hoja de datos )
| Número de pieza | LPC1104 | |
| Descripción | (LPC1102 / LPC1104) 32-bit ARM Cortex-M0 microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC1102/1104
32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB
SRAM
Rev. 7 — 26 September 2013
Product data sheet
1. General description
The LPC1102/1104 are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC1102/1104 operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC1102/1104 includes 32 kB of flash memory, 8 kB of
data memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four
general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.
Remark: The LPC1104 has a revised pinout and contains several features not found in
the LPC1102:
• Two extra GPIO pins (PIO0_1 and PIO0_6).
• Extra match output (CT32B0_MAT2).
• CLKOUT feature.
• Easier re-entry to ISP via PIO0_1.
• SSP0_CLK available on two pins (A1 and A2) to support debugging of SSP
communication.
• Better positioning of the XTALIN pin for easier PCB layout.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug.
System tick timer.
Memory:
32 kB on-chip flash programming memory.
8 kB SRAM.
In-Application Programming (IAP) and In-System Programming (ISP) support via
on-chip bootloader software.
Digital peripherals:
11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors
and programmable open-drain mode.
1 page  
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
LPC1102/1104UK
D
C
B
A
ball A1
1234
index area
002aaf525
Fig 2. Pin configuration WLCSP16 package
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
5 of 43
5 Page 
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.8.1 Features
• Maximum UART data bit rate of 3.125 Mbit/s.
• 16 Byte Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• FIFO control mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
7.9 SPI serial I/O controller
The LPC1102/1104 contain one SPI controller and fully supports SSP features.
The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
Remark: Care must be taken when using the SPI because the SPI clock SCK and the
serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the
SPI is enabled, the serial wire debugger is no longer available (LPC1102 only).
7.9.1 Features
• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.10 10-bit ADC
The LPC1102/1104 contain one ADC. It is a single 10-bit successive approximation ADC
with five channels.
7.10.1 Features
• 10-bit successive approximation ADC.
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
11 of 43
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC1104.PDF ] | |
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