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FOD8321 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FOD8321
Beschreibung Gate Drive Optocoupler
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 19 Seiten
FOD8321 Datasheet, Funktion
May 2012
FOD8321
2.5A Output Current, Gate Drive Optocoupler in
Optoplanar® Wide Body SOP 5-Pin
Features
Fairchild’s Optoplanar® packaging technology
provides reliable and high voltage insulation with
greater than 8mm creepage and clearance distance,
and 0.5mm internal insulation distance while still
offering a compact footprint
2.5A output current driving capability for medium
power IGBT/MOSFET
– Use of P-Channel MOSFETs at output stage
enables output voltage swing close to the supply
rail
20kV/µs Minimum Common Mode Rejection
Wide Supply Voltage range from 15V to 30V
Fast Switching Speed over full operating temperature
range
– 500ns max. propagation delay
– 300ns max. pulse width distortion
UnderVoltage LockOut (UVLO) with hysteresis
Extended industrial temperate range, -40 to 100°C
temperature range
Safety and regulatory approvals
– UL1577, 5,000VRMS for 1 min.
– DIN EN/IEC60747-5-5, 1,414V peak working
insulation voltage
Applications
AC and brushless DC motor drives
Industrial inverter
Uninterruptible power supply
Induction heating
Isolated IGBT/Power MOSFET gate drive
Related Resources
FOD3120, High Noise Immunity, 2.5A Output Current,
Gate Drive Optocoupler Datasheet
Description
The FOD8321 is a 2.5A Output Current Gate Drive
Optocoupler, capable of driving medium power IGBT/
MOSFETs. It is ideally suited for fast switching driving of
power IGBT and MOSFETs used in motor control
inverter applications, and high performance power
systems.
It utilizes Fairchild’s coplanar packaging technology,
Optoplanar®, and optimized IC design to achieve reliably
high insulation voltage and high noise immunity.
It consists of a aluminum gallium arsenide (AlGaAs) light
emitting diode optically coupled to an integrated circuit
with a high-speed driver for push-pull MOSFET output
stage. The device is housed in a wide body 5-pin small
outline plastic package.
Functional Schematic
www.DataSheet.net/
ANODE 1
6 VDD
5 VO
CATHODE 3
4 VSS
©2010 Fairchild Semiconductor Corporation
FOD8321 Rev. 1.0.4
www.fairchildsemi.com
Datasheet pdf - http://www.DataSheet4U.co.kr/






FOD8321 Datasheet, Funktion
Switching Characteristics
Apply over all recommended conditions, typical value is measured at VDD = 30V, VSS = Ground, TA = 25°C unless
otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Units Figure
tPHL Propagation Delay Time to IF = 10mA to 16mA, Rg = 10Ω, 100 285 500 ns 10, 11,
Logic Low Output(9)
Cg =10nF, f = 10kHz,
12, 13,
Duty Cycle = 50%
14, 27
tPLH Propagation Delay Time to
Logic High Output(10)
PWD
PDD
(Skew)
Pulse Width Distortion(11)
|tPHL – tPLH|
Propagation Delay Difference
Between Any Two Parts(12)
100 260 500 ns 10, 11,
12, 13,
14, 27
25 300 ns
-350
350
tR Output Rise Time
(10% to 90%)
60 ns 27
tF Output Fall Time
(90% to 10%)
60 ns 27
tULVO ON
tULVO OFF
|CMH|
|CML|
ULVO Turn On Delay
ULVO Turn Off Delay
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
IF = 10mA, VO > 5V
IF = 10mA, VO < 5V
TA = 25°C, VDD = 30V,
IF = 10 to 16mA, VCM = 2000V(13)
TA = 25°C, VDD = 30V, VF = 0V,
VCM = 2000V(14)
20
20
0.8
0.4
50
50
µs
µs
kV/µs
kV/µs
28
28
Notes:
9. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the
falling edge of the VO signal.
www.DataSheet.net/
10. tPLH propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the
rising edge of the VO signal.
11. PWD is defined as | tPHL – tPLH | for any given device.
12. The difference between tPHL and tPLH between any two FOD8321 parts under same operating conditions, with equal
loads.
13. Common mode transient immunity at output high is the maximum tolerable negative dVcm/dt on the trailing edge of
the common mode impulse signal, Vcm, to assure that the output will remain high (i.e. VO > 15.0V).
14. Common mode transient immunity at output low is the maximum tolerable positive dVcm/dt on the leading edge of
the common pulse signal, Vcm, to assure that the output will remain low (i.e. VO < 1.0V).
©2010 Fairchild Semiconductor Corporation
FOD8321 Rev. 1.0.4
6
www.fairchildsemi.com
Datasheet pdf - http://www.DataSheet4U.co.kr/

6 Page









FOD8321 pdf, datenblatt
Test Circuit (Continued)
1
IF = 10 to 16mA
3
6
0.1μF
5
VO
+
VDD = 30V
4
Figure 22. IDDH Test Circuit
1
+
VF = -3.0 to 0.8V
3
6
0.1μF
5 VO
4
www.DataSheet.net/
Figure 23. IDDL Test Circuit
+
VDD = 30V
©2010 Fairchild Semiconductor Corporation
FOD8321 Rev. 1.0.4
12
www.fairchildsemi.com
Datasheet pdf - http://www.DataSheet4U.co.kr/

12 Page





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