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AD9250 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9250
Beschreibung Dual Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9250 Datasheet, Funktion
Data Sheet
14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9250
FEATURES
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
VIN+A
VIN–A
VCM
VIN+B
VIN–B
SYSREF±
SYNCINB±
CLK±
RFCLK
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD
AGND DGND DRGND
AD9250
PIPELINE
14-BIT ADC
PIPELINE
14-BIT ADC
JESD-204B
INTERFACE
HIGH
SPEED
SERIALIZERS
CONTROL
REGISTERS
CML, TX
OUTPUTS
SERDOUT0±
SERDOUT1±
CMOS
DIGITAL
INPUT/
OUTPUT
PDWN
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
FAST
DETECT
CMOS
DIGITAL
INPUT/
OUTPUT
FDA
FDB
RST
SDIO SCLK CS
Figure 1.
PRODUCT HIGHLIGHTS
www.DataSheet.net/
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide a
single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Datasheet pdf - http://www.DataSheet4U.co.kr/






AD9250 Datasheet, Funktion
AD9250
Data Sheet
Parameter1
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS), 187.12 MHz (−7 dBFS)
CROSSTALK2
FULL POWER BANDWIDTH3
Temperature
25°C
Full
25°C
AD9250-170
AD9250-250
Min Typ Max Min Typ Max
87
95
1000
84
95
1000
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3 Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
Unit
dBc
dB
MHz
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Input CLK± Clock Rate
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
RF CLOCK INPUT (RFCLK)
Input CLK± Clock Rate
Logic Compliance
Internal Bias
Input Voltage Range
Input Voltage Level
High
Low
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance (AC-Coupled)
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
www.DataSheet.net/
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ
Max
40
0.3
AGND
0.9
0
−60
8
625
CMOS/LVDS/LVPECL
0.9
3.6
AVDD
1.4
+60
0
4
10 12
650
AGND
1500
CMOS/LVDS/LVPECL
0.9
AVDD
1.2
AGND
0
−150
8
1
10
AVDD
0.6
+150
0
12
0.3
DGND
0.9
−5
−5
12
LVDS
0.9
1
16
3.6
DVDD
1.4
+5
+5
20
Unit
MHz
V
V p-p
V
V
µA
µA
pF
kΩ
MHz
V
V
V
V
µA
µA
pF
kΩ
V
V p-p
V
V
µA
µA
pF
kΩ
Rev. 0 | Page 6 of 44
Datasheet pdf - http://www.DataSheet4U.co.kr/

6 Page









AD9250 pdf, datenblatt
AD9250
Pin No.
Data Outputs
18
19
21
22
DUT Controls
10
31
32
33
34
Mnemonic
SERDOUT1+
SERDOUT1−
SERDOUT0−
SERDOUT0+
RST
SDIO
SCLK
CS
PDWN
Data Sheet
Type
Description
Output
Output
Output
Output
Lane B CML Output Data—True.
Lane B CML Output Data—Complement.
Lane A CML Output Data—Complement.
Lane A CML Output Data—True.
Input
Input/Output
Input
Input
Input
Digital Reset (Active Low).
SPI Serial Data I/O.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-
down or standby (see Table 17).
www.DataSheet.net/
Rev. 0 | Page 12 of 44
Datasheet pdf - http://www.DataSheet4U.co.kr/

12 Page





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