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PDF LPC4072 Data sheet ( Hoja de datos )
| Número de pieza | LPC4072 | |
| Descripción | (LPC407x / LPC408x) 32-bit ARM Cortex-M4 MCU | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC408x/7x
32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM;
USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI
Rev. 1 — 17 September 2012
Objective data sheet
1. General description
The LPC408x/7x is an ARM Cortex-M4 based digital signal controller for embedded
applications requiring a high level of integration and low power dissipation.
The ARM Cortex-M4 is a next generation core that offers system enhancements such as
low power consumption, enhanced debug features, and a high level of support block
integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard
architecture with separate local instruction and data buses as well as a third bus for
peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core for several
versions of the part.
The LPC408x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC408x/7x is targeted to operate at
up to 120 MHz CPU frequency.
The peripheral complement of the LPC408x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,
External Memory controller (EMC), LCD, Ethernet, USB Device/Host/OTG, an SPI Flash
www.DataSheet.net/
Interface (SPIFI), a General Purpose DMA controller, five UARTs, three SSP controllers,
three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers,
two general purpose PWMs with six outputs each and one motor control PWM, an
ultra-low power RTC with separate battery supply and event recorder, a windowed
watchdog timer, a CRC calculation engine and up to 165 general purpose I/O pins.
The analog peripherals include one eight-channel 12-bit ADC, two analog comparators,
and a DAC.
The pinout of LPC408x/7x is intended to allow pin function compatibility with the
LPC24xx/23xx as well as the LPC178x/7x families.
2. Features and benefits
Functional replacement for LPC23xx/24xx and LPC178x/7x family devices.
ARM Cortex-M4 core:
ARM Cortex-M4 processor, running at frequencies of up to 120 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit (not all versions).
Non-maskable Interrupt (NMI) input.
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC4088
LPC4088FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
LPC4088FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
LPC4088FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4078
LPC4078FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC4078FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
LPC4078FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
LLPC4078FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4078FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm
LPC4076
LPC4076FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm
LPC4076FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4074
LPC4074FBD144 LQFP144
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plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm
LPC4074FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm
LPC4072
LPC4072FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm
Version
SOT459-1
SOT950-1
SOT570-2
SOT486-1
SOT459-1
SOT950-1
SOT570-2
SOT486-1
SOT315-1
SOT570-2
SOT486-1
SOT486-1
SOT315-1
SOT315-1
Table 2. Ordering options
Type number
LPC4088
LPC4088FBD208 512
LPC4088FET208 512
LPC4088FET180 512
LPC4088FBD144 512
LPC4078
LPC4078FBD208 512
LPC4078FET208 512
LPC4078FET180 512
LPC4078FBD144 512
LPC4078FBD80 512
96
96
96
96
96
96
96
96
96
4032
4032
4032
4032
4032
4032
4032
4032
4032
32 yes yes H/O/D 5 yes yes yes yes LQFP208
32 yes yes H/O/D 5 yes yes yes yes TFBGA208
16 yes yes H/O/D 5 yes yes yes yes TFBGA180
8
yes yes H/O/D 5
yes yes yes yes LQFP144
32 no yes H/O/D 5 yes yes yes yes LQFP208
32 no yes H/O/D 5 yes yes yes yes TFBGA208
16 no yes H/O/D 5 yes yes yes yes TFBGA180
8
no yes H/O/D 5
yes yes yes yes LQFP144
-
no yes H/O/D 5
yes yes yes yes LQFP80
LPC408X_7X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 September 2012
© NXP B.V. 2012. All rights reserved.
5 of 123
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5
(EMC pins).
Symbol
Description
P0[4]
P0[5]
P0[6]
168 B12 A11 116 -
166 C12 B11 115 -
164 D13 D11 113 64
[3] I; PU I/O P0[4] — General purpose digital input/output pin.
I/O I2S_RX_SCK — I2S Receive clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I CAN_RD2 — CAN2 receiver input.
I T2_CAP0 — Capture input for Timer 2, channel 0.
- R — Function reserved.
I/O CMP_ROSC — Comparator relaxation oscillator for 555
timer applications.
- R — Function reserved.
O LCD_VD[0] — LCD data.
[3] I; PU I/O P0[5] — General purpose digital input/output pin.
I/O I2S_RX_WS — I2S Receive word select. It is driven by
the master and received by the slave. Corresponds to the
signal WS in the I2S-bus specification.
O CAN_TD2www.DataSheet.net/ — CAN2 transmitter output.
I T2_CAP1 — Capture input for Timer 2, channel 1.
- R — Function reserved.
I CMP_RESET — Comparator reset.
- R — Function reserved.
O LCD_VD[1] — LCD data.
[3] I; PU I/O P0[6] — General purpose digital input/output pin.
I/O I2S_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I/O SSP1_SSEL — Slave Select for SSP1.
O T2_MAT0 — Match output for Timer 2, channel 0.
O U1_RTS — Request to Send output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable
signal for UART1.
I/O CMP_ROSC — Comparator relaxation oscillator for 555
timer applications.
- R — Function reserved.
O LCD_VD[8] — LCD data.
LPC408X_7X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 September 2012
© NXP B.V. 2012. All rights reserved.
11 of 123
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
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