Datenblatt-pdf.com


ISL1903 Schematic ( PDF Datasheet ) - Intersil

Teilenummer ISL1903
Beschreibung Dimmable Buck LED Driver
Hersteller Intersil
Logo Intersil Logo 




Gesamt 19 Seiten
ISL1903 Datasheet, Funktion
Dimmable Buck LED Driver - AC Mains or DC Input LED
Driver
ISL1903
The ISL1903 is a high-performance, critical conduction mode
(CrCM), single-ended buck LED driver controller. It may be used
with DC input converters, but also supports single-stage
conversion of the AC mains to a constant current source with
power factor correction (PFC). The ISL1903 supports buck
converter topologies, such as isolated forward converters or
non-isolated source return buck converters. Operation in CrCM
allows near zero-voltage switching (ZVS) for improved
efficiency while maximizing magnetic core utilization.
The ISL1903 is compatible with both leading and trailing edge
modulated AC mains dimmers. It provides all of the features
required for high-performance dimmable LED ballast designs.
Applications
• Industrial and Commercial LED Lighting
• Retrofit LED Lamps with Triac Dimming
• Universal AC Mains Input LED Retrofit Lamps
• AC or DC Input LED Ballasts
Features
• Excellent LED Current Regulation over Line, Load, and
Temperature
• 0 - 100% Dimming with Leading-Edge (Triac) and
Trailing-Edge Dimmers
• Power Factor Correction for up to 0.995 Power Factor and
less than 20% Harmonic Content
• Critical Conduction Mode (CrCM) Operation for
Quasi-Resonant High Efficiency Performance
• Supports Universal AC Mains Input
• Configurable for PWM or DC Current Dimming Control of
LEDs
• Monitors FET Switching Current for Load Regulation
• Supports Isolated and Non-Isolated Buck Topologies
• Closed Loop Soft-Start for No Overshoot
• OFFREF Feature to Set Dimming Off-Point to Improve Fixture
Performance Matching
• -40°C to +125°C Operation
• Pb-free (RoHS Compliant)
www.DataSheet.net/
EMI Filter
AC Mains
1
VDD
14 DHC
5
CS+
AC 12
OUT 16
ISL1903
8 DELADJ
OC 6
13 GND
VERR 9
3 VREF
RAMP
10
FB 7
IOUT
4
100
90
80
70
60
50
40
30
20
10
0
100 90 80 70 60 50 40 30 20 10
CONDUCTION ANGLE (%)
0
FIGURE 1A. BOOST-RETURN (BUCK) TOPOLOGY
FIGURE 1B. CURRENT vs AC CONDUCTION ANGLE
FIGURE 1. ISL1903 APPLICATION PERFORMANCE
August 10, 2012
FN8285.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.co.kr/






ISL1903 Datasheet, Funktion
Pin Configuration
ISL1903
ISL1903
(16 LD QSOP)
TOP VIEW
1 VDD
OUT 16
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
5 CS+
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
DESCRIPTION
VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to
the VDD and GND pins as possible.
OFFREF
Sets the reference level to disable the driver at light loading. The turn-off reference can be set at any level between 0 and 0.6V,
corresponding to 0 to 100% of output loading. This feature is normally used in triac-based wall dimmer applications to disable
the output before the dimmer becomes unstable due to insufficient holding current.
VREF
The 5.40V reference voltage output having ±100 mV tolerance over line, load and operating temperature. Bypass to GND with
a 0.1µF to 3.3µF low ESR capacitor.
IOUT A voltage signal proportional to the peak switching current used to determine the inductor current.
CS+ The input for the CrCM current sense circuit. This input monitors the winding current or voltage to determine the critical
conduction operating point.
www.DataSheet.net/
OC The input to the load current sensing circuitry and the peak overcurrent comparator. The signal is sampled at the peak current
level for each switching cycle, amplified, and output on IOUT as a DC signal. It must be scaled before application to the FB pin
of the error amplifier (EA). The overcurrent comparator threshold is set at 600mV nominal. Peak OCP performs cycle-by-cycle
over current protection. OCP includes leading-edge-blanking (LEB), which blocks the signal at the beginning of the OUT pulse
for the duration of the blanking period and when the OUT pulse is low.
FB FB is the inverting input to the error amplifier (EA). The feedback signal from IOUT, after being scaled and filtered, is applied
to the error amplifier.
DELADJ
Sets delay before a new switching cycles starts. This adjustment allows the user to delay the next switching cycle until the
switching FET drain-source voltage reaches a minimum value to allow quasi-ZVS (Zero Voltage Switching) operation. A resistor
to ground programs the delay. Pulling DELADJ to VREF disables the CrCM oscillator.
VERR
Output of the error amplifiers and the control voltage input to the inverting input of the PWM comparator. VERR cannot source
current and requires an external pull-up resistor to VREF.
RAMP
This is the input for the sawtooth waveform for the PWM comparator. Using an RC from VREF, a sawtooth waveform is created
for use by the PWM. It is compared to the error amplifier output, Verr, to create the PWM control signal. The RAMP pin is shorted
to GND at the termination of the PWM signal.
OVP Input to detect an overvoltage (OV) condition on the output. Since the control variable is output current, a fault that results in
an open circuit will cause excessive output voltage. The circuit hysteresis is a switched current source that is active when the
OV threshold is exceeded.
AC Input to sense AC voltage presence and amplitude. A resistor divider from the main FET drain and circuit ground or from an
auxiliary winding on the transformer/inductor is used to detect the AC voltage.
GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance
layout is necessary. Ground planes and short traces are highly recommended.
DHC An open drain FET used to load the input voltage to pre-load a triac-based dimmer so that adequate holding current is
maintained.
6 FN8285.0
August 10, 2012
Datasheet pdf - http://www.DataSheet4U.co.kr/

6 Page









ISL1903 pdf, datenblatt
ISL1903
Test Waveforms and Circuits (Continued)
OC THRESHOLD
OC
OUT
LEADING EDGE BLANKING
OC PROPAGATION DELAY
OC + LEB TO OUT DELAY
FIGURE 4. OC +LEB TO OUT DELAY
Typical Performance Curves
1.001
1.000
0.999
0.998
0.997
0.996 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 6. REFERENCE VOLTAGE vs TEMPERATURE
AC
MAINS
tDELAY
tDELAY
DHC
FIGURE 5. AC MAINS TO DHC TIMING
500
400
300
200
100
www.DataSheet.net/
0
0 10 20 30 40 50 60 70 80 90 100
AC CONDUCTION ANGLE (% DUTY CYCLE 120Hz)
FIGURE 7. EA REFERENCE vs AC SIGNAL DUTY CYCLE
2.5
2.0
1.5
1.0
0.5
0 0 25 50 75 100 125 150 175 200 225
DELAY RESISTANCE (k)
FIGURE 8. DELAY vs DELADJ RESISTANCE
100
80
60
40
20
0
0 10 20 30 40 50 60 70 80 90 100
AC CONDUCTION ANGLE (% DUTY CYCLE 120Hz)
FIGURE 9. PWMOUT DUTY CYCLE vs AC SIGNAL DUTY CYCLE
12
FN8285.0
August 10, 2012
Datasheet pdf - http://www.DataSheet4U.co.kr/

12 Page





SeitenGesamt 19 Seiten
PDF Download[ ISL1903 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ISL1903Dimmable Buck LED DriverIntersil
Intersil
ISL1904Dimmable AC Mains LED DriverIntersil
Intersil

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche