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RTL8196C-GR Schematic ( PDF Datasheet ) - Realtek

Teilenummer RTL8196C-GR
Beschreibung IEEE 802.11n AP/ROUTER Network Processor
Hersteller Realtek
Logo Realtek Logo 




Gesamt 45 Seiten
RTL8196C-GR Datasheet, Funktion
ial fileesd toRTL8196C-GR
nfident uthorizIEEE 802.11n AP/ROUTER NETWORK
co a 51PROCESSOR WITH EEE
www.DataSheet.net/
ltek ument T&W 7:17:DATASHEET
a c 1(CONFIDENTIAL: Development Partners Only)
Re he do 7-02 Rev. 1.2
T 0 23 March 2010
- Track ID: JATR-2265-11
010Realtek Semiconductor Corp.
2No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
Datasheet pdf - http://www.DataSheet4U.co.kr/






RTL8196C-GR Datasheet, Funktion
RTL8196C
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ........................................................................................................................................................4
FIGURE 2. PIN ASSIGNMENTS .......................................................................................................................................................5
FIGURE 3. ONE 16-BIT, FOR 1M/2M/4M/8M BYTES FLASH CONFIGURATION............................................................................12
sFIGURE 4. TYPICAL CONNECTION TO A CRYSTAL ......................................................................................................................30
FIGURE 5. TYPICAL CONNECTION TO AN OSCILLATOR...............................................................................................................30
eFIGURE 6. SDRAM CLOCK SPECIFICATIONS-1 ..........................................................................................................................31
lFIGURE 7. SDRAM CLOCK SPECIFICATIONS-2 ..........................................................................................................................31
FIGURE 8. SDRAM INPUT TIMING .............................................................................................................................................32
iFIGURE 9. SDRAM OUTPUT TIMING .........................................................................................................................................32
f oFIGURE 10. SDRAM ACCESS CONTROL TIMING .........................................................................................................................33
tFIGURE 11. FLASH ACCESS TIMING.............................................................................................................................................34
FIGURE 12. POWER UP SEQUENCE TIMING DIAGRAM .................................................................................................................34
lFIGURE 13. POWER UP CONFIGURATION TIMING DIAGRAM........................................................................................................35
RealTtheek dcoocnufmiednetn2t0ai1ua0t-Th0&o7Wr-i0z2ed17:17:51www.DataSheet.net/
IEEE 802.11n AP/Router Network Processor with EEE vi
Track ID: JATR-2265-11 Rev. 1.2
Datasheet pdf - http://www.DataSheet4U.co.kr/

6 Page









RTL8196C-GR pdf, datenblatt
RTL8196C
Datasheet
5. Pin Descriptions
In this section the following abbreviations are used:
I: Input
sO: Output
leIO: Bi-Directional Input/Output
fi oP: Digital Power
tG: Digital Ground
al dT/S: Tri-State Bi-Directional Input/Output
ti zeIPD: Input Pin With Pull-Down Resistor
n iIPU: Input Pin With Pull-Up Resistor;
e r(Typical Value = 75K Ohm)
AI: Analog Input
AO: Analog Output
AI/O: Analog Bi-Directional Input/Output
AP: Analog Power
AG: Analog Ground
S/T/S: Sustained Tri-State
OOD: Output With Open Drain
O3S: Output With Tri-State
nfid uthoPinName
co a 5125M_XI
t :25M_XO
k n 740M_CLK
e e W 140M_SEL
lt um T& 7:RESET#
a c 1TXOP[4:0]
Re do 2TXON[4:0]
RXIP[4:0]
0RXIN[4:0]
he 7-MD[15:0]
T 2010-0MA[21:0]
Table 1. Pin Descriptions
Pin No.
Type Description
Clock & Reset
127 I 25MHz Crystal Clock Input
126
O 25MHz Crystal Clock Outputwww.DataSheet.net/
125 I 40MHz Clock Input Vpeak-to-peak 1.4 Voltage
124 I System Clock Source Select.
0: 25MHz
1: 40MHz
108 I The System Reset Active Low
10M/100Mbps Physical Layer
28, 26, 18, 16, 7
AO 10/100M Ethernet Physical Layer Transmit Pair.
29, 25, 19, 15, 8
For differential data transmission
30, 24, 20, 13, 9
AI 10/100M Ethernet Physical Layer Receive Pair.
31, 23, 21, 12, 8
For differential data reception
Memory Bus
94, 93, 92, 91, 90, 89,
88, 87, 74, 75, 77, 78,
79, 80, 81, 82
I/O Data for SDRAM and NOR Type Flash
48, 47, 46, 45, 43, 85,
72, 63, 65, 57, 56, 62,
55, 53, 52, 51, 50, 49,
58, 59, 60, 61
O Address for SDRAM and NOR Type Flash.
Shared pins:
MA[13]: SDRAM BS0
MA[14]: SDRAM BS1
MA[15]: SDRAM LDQM MA[16]: SDRAM UDQM
MA[17]: SPI Flash SDIO3 MA[18]: SPI Flash SDIO2
MA[19]: SPI Flash SDIO1 MA[20]: SPI Flash SDIO0
MA[21]: SPI Flash SCK
IEEE 802.11n AP/Router Network Processor with EEE 6
Track ID: JATR-2265-11 Rev. 1.2
Datasheet pdf - http://www.DataSheet4U.co.kr/

12 Page





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