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A015AN02 Schematic ( PDF Datasheet ) - AUO

Teilenummer A015AN02
Beschreibung COLOR TFT-LCD MODULE
Hersteller AUO
Logo AUO Logo 




Gesamt 24 Seiten
A015AN02 Datasheet, Funktion
Doc. version : 6
Total pages : 21
Date
: 2002.12.09
Product Specification
1.5 COLOR TFT-LCD MODULE
MODEL NAME: A015AN02
www.DataSheet.co.kr
< >Preliminary Specification
< > Final Specification
Note: The content of this
specification is subject to
change.
© 2002 AU Optronics
All Rights Reserved,
Do Not Copy.
Datasheetpdf-http://www.DataSheet4U.net/






A015AN02 Datasheet, Funktion
Version :
Page :
3
4/ 21
B. Electrical specifications
1.Pin assignment
a. TFT-LCD panel driving section
Pin no Symbol I/O
Description
1
GND
- Ground for logic circuit
Remark
2 VCC P Supply voltage of logic control circuit for scan driver
3 VGL P Negative power for scan driver
4 VGH P Positive power for scan driver
5
FRP
O Gate driver input signal that is fram polarity output for Vcom
6
VCOM
I Common electrode driving signal
7
DRV
VO Power transistor gate signal for the boost converter
8 FB VI Main boost regulator feedback input(FB threshold is 1.2V)
9
SHL
I Left/Right scan control input
Note 1
10 STB I Stand by mode setting pin.
Note 2
11 VCC P Supply voltage for digital circuit
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12
SHDB
I Shutdown input. Active low.
Note 3
13
AGND
P Ground pins for analog circuits
14
VLED
I LED Anode
15
GLED
O LED Cathode
16
AVDD
P Power supply for analog circuits
17
HSYNC
I Horizontal sync input. Negative polarity
18
VSYNC
I Vertical sync input. Negative polarity.
19
DCLK
I Clock signal; latch data onto line latches at the rising edge.
20 D05 I Data input. :MSB
21 D04 I Data input
22 D03 I Data input
23 D02 I Data input
24 D01 I Data input
25 D00 I Data input. :LSB
26
GRB
I Global reset pin.
Note 4
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









A015AN02 pdf, datenblatt
Version :
Page :
3
10/ 21
Fig 2 DCCK block diagram
To reduce the noise affect,CP0 will processed by De-bounce circuit. State-machine will
generate the duty cycle by CP0 signal. To make sure that VFB can reach default VREF quickly, so
State-machine’s is designed as a discrete step by step function. please refer to Fig 3. If CP0 is low ,
Duty cycle will work from 0% to 75%. The maximum duty ratio is 75%.
Fig 3 PWM Control state diagram
b.Shutdown Mode
In shutdown mode, a logic-low level on SHDB, pwm controller and the reference are disabled.
The supply current drops to maximize battery life and the reference is pulled to ground. Every output
voltage will decay. If unused, connect SHDB to VCC.
www.DataSheet.co.kr
c.Oscillator Circuit
The boost-converter operating frequency can be set at 1/16,1/32,1/64 times the system clock,
DCLK. In A015AN02’s model. the DC-DC converter osc frequency is DCLK/64=383.4khz
C. Optical specification (Note 1,Note 2, Note 3 )
Item
Symbol Condition Min. Typ. Max.
Unit
Remark
Response time
Rise Tr
Fall Tf
=0 - 25 50
- 30 60
Contrast ratio
At optimized
CR viewing angle 60
150
-
ms Note 4
ms
Note 5,6
Viewing angle
Top
Bottom
Left
Right
10 -
-
CR 10
30
-
-
deg
Note 7
45 -
45 -
-
-
Brightness
YL
=0
160 200
-
cd/m2
Note 8
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PRPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





SeitenGesamt 24 Seiten
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