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PDF BU9890GUL-W Data sheet ( Hoja de datos )

Número de pieza BU9890GUL-W
Descripción Silicon Monolithic Integrated Circuit
Fabricantes ROHM Semiconductor 
Logotipo ROHM Semiconductor Logotipo



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No Preview Available ! BU9890GUL-W Hoja de datos, Descripción, Manual

STRUCTURE
PRODUCT
PART NUMBER
PHYSICAL DIMENSION
BLOCK DIAGRAM
USE
FEATURES
Silicon Monolithic Integrated Circuit
4K×8 bit Electrically Erasable PROM
BU9890GUL-W
Fig.-1(VCSP50L1)
Fig.-2
General purpose
・4K words × 8 bits architecture serial EEPROM
・Wide operating voltage range (1.7V~3.6V)
・Two wire serial interface
・Self-timed write cycle with automatic erase
・32 byte Page Write mode
・Low power consumption。
Write (3.3V) : 0.6mA (Typ.)
Read (3.6V) : 0.6mA (Typ.)
Standby (3.6V) : 0.1μA (Typ.)
・DATA security
Write protect feature (WP pin)
Inhibit to WRITE at low VCC
・WLCSP 6pin package
・High reliability fine pattern CMOS technology
・Endurance : 100,000 erase/write cycles
・Data retention : 40 years
・Filtered inputs in SCL・SDA for noise suppression
・Initial data FFh in all address
・Pull-up resistor inputs in SCL・SDA
ABSOLUTE MAXIMUM RATING (Ta=25℃
Parameter
Supply Voltage
Symbol
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VCC
Rating
-0.3~6.5
Unit
V
Power Dissipation
Pd
220 *1
mW
Storage Temperature
Tstg
-65~125
Operating Temperature Topr
-40~85
Terminal Voltage
-0.3~Vcc+1.0 *2
V
*1 Degradation is done at 2.2mW/℃(*1) for operation above 25℃
*2 Maximum value of Terminal Voltage is below 6.5V.
1/13
◇RECOMMENDED OPERATING CONDITION
Parameter
Supply Voltage
Write
Read
Input Voltage
Symbol
Vcc
VIN
Rating
2.7~3.3
1.7~3.6
0~Vcc
REV. A
Unit
V
V
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BU9890GUL-W pdf
◇PIN CONFIGURATION
5/13
○ ○ ○B B1 B2
B3
TEST GND VDD
○ ○ A A1 A2 A3
SDA SCL
WP
1 23
◇PIN NAME
Land No.
B3
B2
B1
A3
A2
A1
PIN NAME
Vcc
GND
TEST
WP
SCL
SDA
I/O
-
-
INwww.DataSheet.co.kr
IN
IN
IN/OUT
FUNCTIONS
Power Supply
Ground (0V)
TEST Pin Connect with GND
Write Protect Input
Serial Clock Input
Slave and Word Address,
Serial Data Input, Serial Data Output
REV. A
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BU9890GUL-W arduino
11/13
◇BYTE WRITE
SDA
LINE
SW
TR
A
R
T
SLAVE
ADDRESS
I
T
E
1st WORD
ADDRESS
10100 00
*
*
*
*
WA
11
2nd WORD
ADDRESS
DATA
WA
0
D7
S
T
O
P
D0
RA A A A
/C C C C
WK K K K
WP
* : Dont care
Fig.-8 BYTE WRITE CYCLE TIMING
○By using this command, the data is programed into the indicated word address.
○When the master generates a STOP condition, the device begins the internal
write cycle to the nonvolatile memory array.
SDA
LINE
WP
SW
TR
A
R
T
SLAVE
ADDRESS
I
T
E
1st WORD
ADDRESS(n)
2nd WORD
ADDRESS(n)
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DATA(n)
DATA(n+31)
S
T
O
P
1 0 10 0 0 0
*
*
*
*
WA
11
WA
0 D7
D0
D0
RA A A A A
/C C C C C
WK K K K K
* : Dont care
Fig.-9 PAGE WRITE CYCLE TIMING
○This device is capable of thirty-two byte Page Write operation.
○When two or more byte data are inputted, the five low order address(WA4~WA0) bits are in
ternally incremented by one after the receipt of each word. The seven higher order bits of
the address(WA4~WA0) remain constant.
REV. A
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