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PDF W682310 Data sheet ( Hoja de datos )
| Número de pieza | W682310 | |
| Descripción | (W682510 / W682310) Dual-Channel Voiceband Codecs | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de W682310 (archivo pdf) en la parte inferior de esta página. Total 33 Páginas | ||
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W682510/W682310
W682510/ W682310
DUAL-CHANNEL
VOICEBAND CODECS
www.DataSheet.co.kr
Datasheet
Revision A11
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
W682510/W682310
8. TIMING DIAGRAMS.......................................................................................................................... 16
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21
10.1. General Parameters W682510 4.5V – 5.5V........................................................................ 21
10.2. General Parameters W682310 2.7V – 3.8V........................................................................ 21
10.3. Analog Signal Level and Gain Parameters .............................................................................. 23
10.4. Analog Distortion and Noise Parameters ................................................................................. 24
10.5. Analog Input and Output Amplifier Parameters........................................................................ 25
10.6. Digital I/O .................................................................................................................................. 26
11. TYPICAL APPLICATION CIRCUIT................................................................................................. 29
12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 30
12.1. 20L SSOP – 209 mil Shrink Small Outline Package Dimensions ............................................ 30
12.3. 24 SOP – 300 mil...................................................................................................................... 31
13. ORDERING INFORMATION........................................................................................................... 32
14. VERSION HISTORY ....................................................................................................................... 33
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-5-
Publication Release Date: January 2009
Revision A11
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
W682510/W682310
7.1.2. PCMT1
The PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is
sent from PCMT1 in a sequential order, synchronizing with the rising edge of the BCLK signal. The
MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST.
This output pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power-saving state or power-down. When serial operation is selected, this pin
is configured to be the output of the serial multiplexed two channel PCM signal. A pull-up resistor must
be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding
law and output coding format recommendation.
Level
+ Full Scale
+ Zero
- Zero
- Full Scale
TABLE 7.15: PCM CODES FOR ZERO AND FULL SCALE
μ-Law
A-Law
Sign bit Chord bits Step bits Sign Bit Chord Bits
1
000 0000
1
010
1
111 1111
1
101
0
111 1111
0
101
0
000 0000
0
010
Step Bits
1010
0101
0101
1010
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7.1.3. PCMT2
The PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is
sent from PCMT2 in a sequential order, synchronized with the rising edge of the BCLK signal. The
MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance
state during power-saving state or power-down. When the serial operation is selected, this pin is left
open. A pull-up resistor must be connected to this pin , as it is an open drain output. This device is
compatible with the ITU-T coding law and output coding format recommendation.
7.2. RECEIVE PATH
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO.
7.2.1. RO1, RO2
RO1 and RO2 are the receive analog outputs for channel 1 and channel 2. The output signal of the
W682510 has an amplitude of 3.46 Vpp (2.03 Vpp for W682310) around the signal ground voltage
(VREF). When the digital PCM signal of +3 dBm0 is presented to PCMR1 or PCMR2, it can drive a load
- 11 -
Publication Release Date: January 2009
Revision A11
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet W682310.PDF ] | |
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