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PDF W6810 Data sheet ( Hoja de datos )
| Número de pieza | W6810 | |
| Descripción | SINGLE CHANNEL VOICECODEC | |
| Fabricantes | Nuvoton Technology | |
| Logotipo |  |
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W6810 SINGLE CHANNEL VOICECODEC
1. GENERAL DESCRIPTION
The W6810 is a general-purpose single channel PCM CODEC with pin-selectable -Law or A-Law companding.
The device is compliant with the ITU G.712 specification. It operates off of a single +5V power supply and is
available in 20-pin SOG, SSOP, and TSSOP package options.. Functions performed include digitization and
reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are
compliant with ITU G.712 specification. W6810 performance is specified over the industrial temperature range of
–40C to +85C.
The W6810 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving
300 loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise
and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-
frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN
applications. W6810 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-
scaler automatically determines the division ratio for the required internal clock.
For fast evaluation and prototyping purposes, the W6810DK development kit is available.
2. FEATURES
Single +5V power supply
Typical power dissipation of 25 mW, power-
down mode of 0.5 W
Fully-differential analog circuit design
On-chip precision reference of 1.575 V for a 0
dBm TLP at 600 (775mVRMS)
Push-pull power amplifiers with external gain
adjustment with 300 load capability
Seven master clock rates of 256 kHz to 4.096
MHz
Pin-selectable -Law and A-Law companding
(compliant with ITU G.711)
CODEC A/D and D/A filtering compliant with
ITU G.712
Industrial temperature range (–40C to +85C)
Three packages: 20-pin SOG, SSOP, and
TSSOP
Pb-Free / RoHS package options available
ApplIcations
www.DataSheet.co.kr
Digital Telephone Systems
Central Office Equipment (Gateways, Switches,
Routers)
PBX Systems (Gateways, Switches)
PABX/SOHO Systems
Local Loop card
SOHO Routers
VoIP Terminals
Enterprise Phones
ISDN Terminals
Analog line cards
Digital Voice Recorder
Revision A16
-1-
January 2011
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
W6810 SINGLE CHANNEL VOICECODEC
5. PIN CONFIGURATION
1 VREF
2 RO-
VAG
AI+
3 PAI
AI-
4 PAO-
AO
5 PAO+
W6810
u/A Law
Single Channel
6 VDD
Voice Codec
VSS
7 FSR
FST
8 PCMR
PCMT
9 BCLKR
10 PUI
www.DataSheet.co.kr
BCLKT
MCLK
20
19
18
17
16
15
14
13
12
11
Revision A16
-5-
January 2011
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
W6810 SINGLE CHANNEL VOICECODEC
BCLKR (Pin 9)
FSR (Pin 7) Interface Mode
64 kHz to 4.096 MHz
8 kHz
Long or Short Frame Sync
VSS VSS ISDN GCI with active channel B1
VSS VDD ISDN GCI with active channel B2
VDD VSS ISDN IDL with active channel B1
VDD VDD ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT
pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device
synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame
Sync signal. It recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling edges
of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as
the positive frame sync edge occurs every 125 sec. During data transmission in the Long Frame Sync mode,
the transmit data pin PCMT will become low impedance whenwww.DataSheet.co.kr the Frame Sync signal FST is HIGH or when the 8
bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame
Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The internal
decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous
frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after
every power down state. More detailed timing information can be found in the interface timing section.
7.4.2. Short Frame Sync
The W6810 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and
only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W6810
starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data
transmit pin PCMT will go back to the high impedance state halfway the LSB. The Short Frame Sync operation of
the W6810 is based on an 8-bit data word. When receiving data on the PCMR pin, the data is clocked in on the
first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will
determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down
state. More detailed timing information can be found in the interface timing section.
Revision A16
- 11 -
January 2011
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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