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PDF LT3692 Data sheet ( Hoja de datos )
| Número de pieza | LT3692 | |
| Descripción | Monolithic Dual Tracking 3.5A Step-Down Switching Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Wide Input Range:
– Operation from 3V to 36V
– OVLO Protects Circuit Through 60V Transients
n Independent Supply, Shutdown, Soft-Start,
Programmable Current Limit and Programmable
Power Good for Each 3.5A Regulator
n Die Temperature Monitor
n Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2.25MHz with
Synchronized Clock Output
n Independent Synchronized Switching Frequencies
Optimize Component Size
n Antiphase Switching
n Outputs Can Be Paralleled
n Flexible Output Voltage Tracking
n Enhanced Short-Circuit Protection
n Low Dropout: 95% Maximum Duty Cycle
n 5mm × 5mm QFN Package
APPLICATIONS
n Automotive Supplies
n Distributed Supply Regulation
LT3692
Monolithic Dual Tracking
3.5A Step-Down
Switching Regulator
DESCRIPTION
The LT®3692 is a dual current mode PWM step-down
DC/DC converter with two internal 3.8A switches. Indepen-
dent input voltage, shutdown, feedback, soft-start, current
limit and comparator pins for each channel simplify com-
plex power supply tracking and sequencing requirements.
To optimize efficiency and component size, both convert-
ers have a programmable maximum current limit and are
synchronized to either a common external clock input,
or a resistor settable fixed 250kHz to 2.25MHz internal
oscillator. A frequency divider is provided for channel 1
to further optimize component size. At all frequencies, a
180° phase relationship between channels is maintained,
reducing voltage ripple and component size. A clock output
is available for synchronizing multiple regulators.
Minimum input to output voltage ratios are improved by
allowing the switch to stay on through multiple clock cycles
only switching off when the boost capacitor needs recharg-
ing. Independent channel operation can be programmed
using the SHDN pin. Disabling both converters reduces
the total quiescent to <10µA.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
TYPICAL APPLICATION
Independent Synchronized Switching Frequencies
Extend Full Frequency Input Range
VIN
6V TO 32V
Dual 1.8V/3.5A and 5V/3.5A Step-Down Converter
VOUT2
VOUT1
1.8V 3.5A
500kHz/
250kHz
143k
7.15k
0.47µF
100µF
×2 8.06k
60.4k
60.4k
47pF
4.7µF
×2
VIN1
SHDN1
BST1
VIN2
SHDN2
BST2
6.8µH SW1
SW2
IND1
IND2
LT3692
VOUT1
VOUT2
10k FB1 FB2
CMPI1
CMPI2
CMPO1 CMPO2
SS2 SS1
SS2
ILIM2 ILIM1
ILIM2
DIV CLKOUT
680pF
17.8k
VC1
RT/SYNC
GND
13.0k
VC2
TJ
0.1µF
6.8µH
42.2k 8.06k
1µF
100k
VOUT2
5V 3.5A
47µF 500kHz
PG2
CLOCKOUT
500kHz
330pF
36.5k
60.4k
33pF
0.1µF
3692 TA01a
CLKOUT
SW1
SW2
VIN = 12V
1µs/DIV
CLKOUT
SW1
SW2
VIN = 24V
1µs/DIV
3692 TA01b
3692 TA01c
3692f
1
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TYPICAL PERFORMANCE CHARACTERISTICS
LT3692
Shutdown Threshold and Minimum
Input Voltage vs Temperature
3.5
3.0 MINIMUM
INPUT VOLTAGE
2.5
2.0
SHUTDOWN
1.5 THRESHOLD VOLTAGE
1.0
0.5
0
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G01
Shutdown Quiescent Current
vs Temperature
10
9
8
7 IQ1
6
5
4
3
2
1
0
–50 –25
IQ2
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G05
Error Amplifier Transconductance
vs Temperature
425
420
415
410
405
400
395
390
385
380
375
370
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
3692 G08
Shutdown Pin Input Current
vs Temperature
50
45
40
35
VIN = 15V
VSHDN = 15V
30
25
20
15
10
5
0
–50 –25
VIN = 15V
VSHDN = 1.3V
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G02
FB Voltage and CH1-CH2 FB
Offset vs Temperature
820
8
6
815 4
OFFSET
810
2
0
CH2
805 CH1
–2
–4
–6
800
–50 –25
–8
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G06
Soft-Start-to-Feedback Offset
vs Temperature
4 VSS = 0.4V
3
2
1
0
–1
–2
–3
–4
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G09
vVsINTOemveprevroalttaugree Threshold
40.0
39.5
39.0
38.5
38.0
37.5
37.0
36.5
36.0
35.5
35.0
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G04
TJ Output Voltage vs Temperature
1.50
1.25
1.00
0.75
0.50
0.25 RTJ = 30k
TO GND
0
–0.25
RTJ = 30k TO –1V
–0.50
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G07
Comparator Thresholds
vs Temperature
750
740
730 RISING
720 THRESHOLD
710
700
690
680
670
FALLING
THRESHOLD
660
650
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3692 G10
3692f
5
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LT3692
BLOCK DIAGRAM
In addition, the internal slope compensation will be au-
tomatically adjusted to prevent subharmonic oscillation
during synchronization. In either mode of oscillator op-
eration, a square wave with the master clock frequency,
synchronized to channel 1 is present at the CLKOUT pin.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
the normal error amplifier, there is a current sense amplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
When, during power-up, an internal POR signal sets the
soft-start latch, both SS pins will be discharged to ground
to ensure proper start-up operation. When the SS pin volt-
age drops below 90mV, the VC pin is driven low disabling
switching and the soft-start latch is reset. Once the latch
is reset the soft-start capacitor starts to charge with a
typical value of 12µA.
As the voltage rises above 115mV on the SS pin, the VC
pin will be driven high by the error amplifier. When the
voltage on the VC pin exceeds 0.8V, the clock set-pulse sets
the driver flip-flop, which turns on the internal power NPN
switch. This causes current from VIN, through the NPN
switch, inductor and internal sense resistor to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
VC pin, the flip-flop is reset and the internal NPN switch
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceeds the predetermined level at the start of a clock cycle,
the flip-flop will not be set resulting in a further decrease
in inductor current. Since the output current is controlled
by the VC voltage, output regulation is achieved by the
error amplifier continually adjusting the VC pin voltage.
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 806mV reference. Compen-
sation of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the VC pin to ground.
The regulators’ maximum output current occurs when the
VC pin is driven to its maximum clamp value by the error
amplifier. The value of the maximum switch current can be
programmed from 4.8A to 2A by placing a resistor from
the ILIM pin to ground.
Since the SS pin is driven by a constant current source, a
single capacitor on the soft-start pin will generate controlled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the VC pin clamp, the SS pin
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
Once the overload condition is removed, the regulator will
soft-start from the overload regulation point.
Shutdown control, VIN overvoltage, or thermal shutdown
will set the soft-start latch, resulting in a complete soft-
start sequence.
The switch driver operates from either the VIN or BST volt-
age. An external diode and capacitor are used to generate
a drive voltage higher than VIN to saturate the output NPN
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
3692f
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LT3692.PDF ] | |
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