UM10430 Datasheet PDF - NXP Semiconductors
| Part Number | UM10430 | |
| Description | LPC18xx ARM Cortex-M3 microcontroller | |
| Manufacturers | NXP Semiconductors | |
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UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 2.8 — 10 December 2015
User manual
Document information
Info Content
Keywords
LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x,
LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20,
LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3,
SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual
Abstract
LPC18xx user manual
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NXP Semiconductors
UM10430
Chapter :
Revision history …continued
Rev
Date
Description
Modifications:
• Table 700 “SCT configuration example” corrected.
• Number of EMC_CS and EMC_DYCS pins corrected for the LQFP208 pin package in Table 343
“EMC pinout for different packages”.
• Section 38.7.5.1 “USART clock in synchronous mode” added.
• Bit 12 changed to 1 for EMC address mapping 256 Mb, 512 Mb, 1 Gb. See Table 367 “Address
mapping”.
• Bit description of bits TSEG1 and TSEG2 corrected in Table 976 “CAN bit timing register (BT,
address 0x400E 200C (C_CAN0) and 0x400A 400C (C_CAN1)) bit description” and Figure 172 “Bit
timing” updated for clarification.
• Parts MX1635E, W25Q16DV, W25Q32FV added to Table 19 “QSPI devices supported by the boot
code and the SPIFI API”.
• Use of IAP calls clarified: IAP commands are not supported for flash-less parts. See Section 5.8 “IAP
commands”.
• For flashless parts only: Unique part ID is stored in OTP bank 0, word 2 and readable at memory
location 0x4004 5008. See Section 3.1 and Table 9 “OTP memory description (OTP base address
0x4004 5000)”.
• For secure parts only: Chapter 7 “LPC18xx Boot ROM for secure parts” added.
• For secure parts only: AES DMA request lines added. See Table 92, Table 252, and Table 272.
• Boot ROM chapter split into two chapters for secure and non-secure parts. See Chapter 4 “LPC18xx
Boot ROM” and Chapter 7 “LPC18xx Boot ROM for secure parts”.
• Description of USB0_DM and USB1_DM pins corrected: These pins do not contain an internal
pull-up. See Table 381 and Table 443.
• Section 4.1.1 “Determine the boot code version” added.
• Signal polarity of signals EMC_CKEOUT and EMC_DQMOUT corrected in Table 346 “EMC pin
description”. Both signals are active HIGH.
• Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 335 “SPIFI control register (CTRL,
address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in
this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
• Bit 4 changed from Reserved to SEE (System Error Enable) in register USBINTR_D and
USBINTR_H . See Table 395 and Table 396.
• Bit 4 changed from Reserved to SEI in register USBSTS_D and USBSTS_H. See Table 393 and
Table 394.
• Bit 4 changed from Reserved to SEE (System Error Enable) register USBINTR_D and USBINTR_H.
See Table 456 and Table 457.
• Bit 4 changed from Reserved to SEI register USBSTS_D and USBSTS_H. See Table 454 and
Table 455.
• Added Section 23.11, System error.
• Removed BUS_RST from Table 153.
• Added a remark on how to read the FLADJ register in Section 10.4.10 and Section 10.4.11.
• Added text: The USART3 boot mode is not supported for LPC18Sxx parts. See Section 4.1, Table 15,
Table 16, and Section 7.1
UM10430
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 2.8 — 10 December 2015
© NXP B.V. 2015. All rights reserved.
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ UM10430.PDF Datasheet ] | |
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