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PDF MR27V6466F Data sheet ( Hoja de datos )
| Número de pieza | MR27V6466F | |
| Descripción | Synchronous One Time PROM | |
| Fabricantes | OKI electronic | |
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PEDR27V6466F-01-08
1Semiconductor
MR27V6466F
This version: Jul. 2001
Previous version: Jun. 2001
Preliminary
4,194,304-Word x 16-Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM
GENERAL DESCRIPTION
The MR27V6466F is a 64 Mbit One Time Programmable Synchronous Read Only Memory whose configuration
can be electrically switched between 4,194,304 x 16 bit (word mode) and 2,097,152 x 32 bit (double word mode)
by the state of the WORD pin. The MR27V6466F supports high speed synchronous read operation using a single
3.3 V power supply.
FEATURES ON READ
• 3.3 V power supply
• LVTTL compatible with multiplexed address
• Dual electrically switchable configuration
4M x 16 (word mode) / 2M x 32 (double word mode)
• All inputs are sampled at the rising edge of the system clock.
• High speed read operation
100 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles
66 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles
50 MHz : CAS Latency = 4, 5, 6 tRCD min: 1 clock cycles
Burst length (4, 8)
Data scramble (sequential, interleave)
• DQM for data out masking
• No Precharge operation is required. No Refresh operation is required.
• No power on sequence is required.
Mode register is automatically initialized to the default state after power on.
“Row Active” or “Mode Register Set” command is applicable as the first command just after power on.
• Single Bank operation
• Package: TSOP(2)86-P-400-0.50-K (Product Name : MR27V6466FTA)
FEATURES ON PROGRAMMING
• 8.0 V programming power supply
• Programming algorithm is compatible with conventional asynchronous OTP.
MR27V6466F can be programmed with conventional EPROM programmers.
Synchronous Burst read or Static Programming Operation is selected by the state of STO pin.
High STO level enables full static programming. (Program, Program Verify, Asynchronous Read)
Low STO level enables synchronous burst read.
Exclusive 86-pin socket adapters are available from OKI to support programming requirements.
The socket adapter is used on a 48-DIP socket on the programmer.
The socket adapter for 64M synchronous OTP is distinguished from the socket adapter for 32M SOTP.
The socket adapter is designed with the STO pin connected to VCC in order to program MR27V6466F as
conventional OTP.
EPROM programmer must have the algorithm for MR27V6466F on the exclusive socket adapter.
*Device damage can occur if improper algorithm is used.
• Programming with address multiplexed input is also available.
• High speed programming
25 µs programming pulse per word allows high speed programming.
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1Semiconductor
PEDR27V6466F-01-08
MR27V6466F
PIN FUNCTION FOR PROGRAMMING OPERATION
(STO pin is high level)
Pin Name
STO
AMPX
A0 to A12
RAS
CAS
DQ0 to DQ15
WORD
CAP0 to
CAP8
OE
CE
VCC/VSS
VCCQ/VSSQ
Vpp
Function
Static Operation
Address Multiplex
Address
Row Address Strobe
Column Address Atrobe
Data Input/Output
x32/x16 Organization Selection
Address Input
Output Enable
Chip Enable
Power Supply/Ground
Data Output Power/Ground
Program Power Supply
Description
Must be set high for programming operation. Internal
resistance (around 10 k ohms) pulls the input level down to VSS
for open state condition to be low level for synchronous read
operation.
When AMPX is low, the addresses are not multiplexed and all
address bits must be supplied to A0 to A12 (Row Address) and
CAP0 to CAP8 (Column Address) simultaneously.
When AMPX is high, multiplexed address inputs are enabled
on A0 to A12.
Row address input.
When AMPX is high, row address is latched at the rising egde
of RAS.
When AMPX is low, input is not used.
When AMPX is high, column address is latched at the rising
egde of CAS.
When AMPX is low, input is not used.
Input of data for programming and output for program verify
and read data.
The WORD pin defines the organization to be x16 (word
mode) or x32 (double word mode).
High = x32
Low = x16
This pin must be set low for programming operation.
When WORD is low, High-Z state on CAP0 to CAP8 is held to
be input pins.
When AMPX is low, column address input.
When AMPX is high, input is not used.
Control signal input for programming.
OE of conventional OTPs.
Control signal input for programming.
Function for programming is associated with conventional
OTPs.
Power and ground for the input buffers and the core logic.
Power and ground for output.
High voltage program power is supplied through VPP pin.
When VPP is higher than a predetermined voltage level
between VCC + 0.5 V and VCC + 2 V, pin function alters to high
VPP mode. To keep stable static read operation VPP pin must
be kept lower than VCC + 0.5 V.
The persons who design socket adapter or make programming algorithm on the condition of omitting socket adapter
provided with OKI study this table. Other persons can ignore this table.
The functionality of programming must be checked with the specification of socket adapter that will be supplied by
OKI. MR27V6466F on the socket adapter is the same programming functionality as conventional OTPs.
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1Semiconductor
PEDR27V6466F-01-08
MR27V6466F
READ OPERATIONS
CAS Latency
After sampling "Read" command, MR27V6466F starts actual data read operation with sense amplifiers, and
transmits the data from sense amplifiers to data out buffers to start burst read. This flow of sequential functionality
takes time as clock cycles defined as CAS latency (CL). CAS latency can be set in Mode Register between from
four cycles to six cycles. In this sequence (from sampling "Read" command to start of driving data bus), sense
amplifiers consume maximum current flow. The detailed sequence is as shown below.
1. Fix the column address of memory matrix driver. Row address is already fixed with "Row Active" command.
(at 1st cycle)
2. Read the data of selected memory cells with sense amplifiers.
3. Deliver the data detected with sense amplifiers to the register for data output latch.
4. Couple selectively the section of the register storing each (double) word to output buffers.
5. Enable the output buffers to drive data bus (at CL-1 cycle).
6. Data the output on data bus can be sampled at the rising edge of system clock at CL cycle.
New "Row Active" command or new "Read" command can be sampled to perform gapless burst read at CL-1
clock cycle of the last "Read" command. New command preceeding CL-1 cycle interrupts sense amplifiers to read
the data at the selected memory cells of the last "Read" command. Interrupted "Read" command perishes or
outputs invalid data before the starting of the data burst of new "Read" command. Refer to the timing chart of
"Burst Read/Interrupt I" and "Burst Read/Interrupt II".
Burst Read
Data outputs are consecutive during the cycle number defined as Burst Length (BL). The latest burst read is
completed unless any interruption such as "Precharge" command stops the sequential data output. Burst Length is
set in Mode Register as either four or eight. After sampling of "Read" command, the first output can be read at the
cycle delayed by CAS latency. Burst Type is also stored in Mode register as either sequential or interleave. The
output buffers go into a high impedance state after burst read sequence is finished, unless a new "Read" command
has been sampled to perform gapless read or preemptive read. Burst read can be interrupted by "Burst Stop"
command or "Precharge" command at the cycle delayed by CAS latency from the command. On condition that
reading data with sense amplifiers of preceding "Read" command is not interrupted by new "Read" command or
"Row active" command, burst read of preceding "Read" command is continued regularly until the burst data
sequence of the new "Read" command starts. The new (latest) burst data sequence always starts regularly.
DQM
Input level on DQM is sampled at the rising edge of system clock to mask data at two cycles later. The output of
masked data is in a high-Z state.
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