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Teilenummer | P30NF10 |
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Beschreibung | STP30NF10 | |
Hersteller | STMicroelectronics | |
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Gesamt 11 Seiten www.DataSheet.co.kr
STB30NF10
STP30NF10 STP30NF10FP
N-CHANNEL 100V - 0.038 Ω - 35A TO-220/TO-220FP/D2PAK
LOW GATE CHARGE STripFET™ II POWER MOSFET
TYPE
VDSS
RDS(on)
ID
STB30NF10
STP30NF10
STP30NF10FP
100 V
100 V
100 V
<0.045 Ω
<0.045 Ω
<0.045 Ω
35 A
35 A
18 A
s TYPICAL RDS(on) = 0.038 Ω
s EXCEPTIONAL dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s APPLICATION ORIENTED
CHARACTERIZATION
s SURFACE-MOUNTING D2PAK (TO-263)
POWER PACKAGE IN TUBE (NO SUFFIX) OR
IN TAPE & REEL (SUFFIX “T4”)
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalanche characteristics and
less critical alignment steps therefore a remark-
able manufacturing reproducibility.
APPLICATIONS
s HIGH-EFFICIENCY DC-DC CONVERTERS
s UPS AND MOTOR CONTROL
3
2
1
TO-220FP
3
1
D2PAK
TO-263
(Suffix “T4”)
3
2
1
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR
Drain-gate Voltage (RGS = 20 kΩ)
VGS Gate- source Voltage
ID Drain Current (continuous) at TC = 25°C
ID Drain Current (continuous) at TC = 100°C
IDM(•) Drain Current (pulsed)
Ptot Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
EAS (2) Single Pulse Avalanche Energy
VISO
Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Operating Junction Temperature
(•) Pulse width limited by safe operating area.
May 2002
.
STB30NF10
STP30NF10
35
25
140
115
0.77
------
Value
STP30NF10FP
100
100
± 20
18
13
72
30
0.2
28
275
2000
Unit
V
V
V
A
A
A
W
W/°C
V/ns
mJ
V
-55 to 175
°C
(1) ISD ≤30A, di/dt ≤400A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
(2) Starting Tj = 25 oC, ID = 15A, VDD= 30V
1/11
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
STB30NF10 STP30NF10 STP30NF10FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/11
Datasheet pdf - http://www.DataSheet4U.net/
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ P30NF10 Schematic.PDF ] |
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