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ZL2101 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ZL2101
Beschreibung 6A Digital Synchronous Step-Down DC/DC Converter
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 27 Seiten
ZL2101 Datasheet, Funktion
www.DataSheet.co.kr
6A Digital Synchronous Step-Down DC/DC Converter
with Auto Compensation
ZL2101
The ZL2101 is a 6A digital converter with auto compensation and
integrated power management that combines an integrated
synchronous step-down DC/DC converter with key power
management functions in a small package, resulting in a flexible
and integrated solution.
The ZL2101 can provide an output voltage from 0.54V to 5.5V
(with margin) from an input voltage between 4.5V and 14V.
Internal low rDS(ON) synchronous power MOSFETs enable the
ZL2101 to deliver continuous loads up to 6A with high efficiency.
An internal Schottky bootstrap diode reduces discrete
component count. The ZL2101 also supports phase spreading to
reduce system input capacitance.
Power management features such as digital soft-start delay and
ramp, sequencing, tracking, and margining can be configured by
simple pin-strapping or through an on-chip serial port. The
ZL2101 uses the PMBus™ protocol for communication with a
host controller and the Digital-DC bus for interoperability
between other Zilker Labs devices.
Features
• Integrated MOSFET Switches
• 6A Continuous Output Current
• ±1% Output Voltage Accuracy
• Auto Compensation
Snapshot™ Parametric Capture
• I2C/SMBus Interface, PMBus Compatible
• Internal Non-Volatile Memory (NVM)
Applications
• Telecom, Networking, Storage equipment
• Test and Measurement Equipment
• Industrial Control Equipment
• 5V and 12V Distributed Power Systems
Related Literature
AN2010 “Thermal and Layout Guidelines for Digital-DC™
Products”
AN2033 “Zilker Labs PMBus Command Set - DDC Products”
AN2035 “Compensation Using CompZL™”
100
VOUT = 3.3V
90
80
70
60
VIN = 12V
50 fSW = 200kHz
L = 6µH
40
0.0 1.0 2.0 3.0 4.0
IOUT (A)
FIGURE 1. ZL2101 EFFICIENCY
5.0
6.0
January 23, 2012
FN7730.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Datasheet pdf - http://www.DataSheet4U.net/






ZL2101 Datasheet, Funktion
www.DataSheet.co.kr
ZL2101
Absolute Maximum Ratings
DC Supply Voltage for VDDP, VDDS Pins . . . . . . . . . . . . . . . . . . -0.3V to 17V
High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
High-Side Boost Voltage for BST - SW Pins . . . . . . . . . . . . . . . . . -0.3V to 8V
Internal MOSFET Reference for VR Pin . . . . . . . . . . . . . . . . . . -0.3V to 8.5V
Internal Analog Reference for VRA Pin . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
Internal 2.5V Reference for V2P5 Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Logic I/O Voltage for EN, CFG, DDC, FC, MGN, PG, SDA, SCL,
SA, SALRT, SS, SYNC, VTRK, VSET, VSEN Pins . . . . . . . . . . -0.3V to 6.5V
Ground Differential for DGND - SGND,
PGND - SGND Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
MOSFET Drive Reference Current for VR Pin
Internal Bias Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Switch Node Current for SW Pin
Peak (Sink Or Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD78C)
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
36 Ld QFN (Notes 6, 7) . . . . . . . . . . . . . . . .
28
1.7
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Dissipation Limits (Note 8)
TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W
TA = +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W
TA = +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4W
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Supply Voltage Range, VDDP, VDDS (See Figure 14)
VDDS tied to VR, VRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
VDDS tied to VR, VRA Floating . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 7.5V
VR, VRA Floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5V to 14V
Output Voltage Range, VOUT (Note 9) . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, TJ . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Thermal impedance depends on layout.
9. Includes margin limits.
Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted. (Note 10) Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITIONS
MIN MAX
(Note 20)
TYP
(Note 20)
UNIT
INPUT AND SUPPLY CHARACTERISTICS
IDD Supply Current
IDDS Shutdown Current
VR Reference Output Voltage
VRA Reference Output Voltage
V2P5 Reference Output Voltage
OUTPUT CHARACTERISTICS
fSW = 200kHz, no load
fSW = 1MHz, no load
EN = 0V, No I2C/SMBus activity
VDD > 8V, IVR < 10mA
VDD > 5.5V, IVRA < 20mA
IV2P5 < 20mA
- 11 20 mA
- 15 30 mA
- 0.6 1 mA
6.5 7.0 7.5
V
4.5 5.1 5.5
V
2.25 2.5 2.75
V
Output Current
Output Voltage Adjustment Range (Note 11)
Output Voltage Setpoint Resolution
IRMS, Continuous
VIN > VOUT
Set using resistors
- - 6A
0.6 - 5.0 V
- 10 - mV
Set using I2C/SMBus
- ±0.025 -
% FS
(Note 12)
VSEN Output Voltage Accuracy
Includes line, load, temp
-1 - 1 %
VSEN Input Bias Current
VSEN = 5.5V
-
110 200
µA
Soft-start Delay Duration Range (Note 13)
Set using SS pin or resistor
2 - 20 ms
Set using I2C/SMBus
0.002
-
500 s
6 FN7730.0
January 23, 2012
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









ZL2101 pdf, datenblatt
www.DataSheet.co.kr
ZL2101
RESISTOR SETTINGS
This method allows a greater range of adjustability when
connecting a finite value resistor (in a specified range) between
the multi-mode pin and SGND.
Standard 1% resistor values are used, and only every fourth E96
resistor value is used so the device can reliably recognize the
value of resistance connected to the pin while eliminating the
error associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
I2C/SMBUS METHOD
ZL2101 functions can be configured via the I2C/SMBus interface
using standard PMBus commands. Additionally, any value that
has been configured using the pin-strap or resistor setting
methods can also be re-configured and/or verified via the
I2C/SMBus. See Application Note AN2033 for more details.
The SMBus device address and VOUT_MAX are the only
parameters that must be set by external pins. All other device
parameters can be set via the I2C/SMBus. The device address is
set using the SA pin. VOUT_MAX is determined as 10% greater
than the voltage set by the VSET pin.
Resistor pin-straps are recommended to be used for all available
device parameters to allow a safe initial power-up before
configuration is stored via the I2C/SMBus. For example, this can
be accomplished by pin-strapping the undervoltage lockout
threshold (using SS pin) to a value greater than the expected
input voltage, thus preventing the device from enabling prior to
loading a configuration file.
Power Conversion Functional
Description
Internal Bias Regulators and Input Supply
Connections
The ZL2101 employs three internal low dropout (LDO) regulators
to supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
follows:
• VR: The VR LDO provides a regulated 7V bias supply for the
high-side MOSFET driver circuit. It is powered from the VDDS
pin and supplies bias current internally. A 4.7µF filter capacitor
is required at the VR pin. The VDDS pin directly supplies the
low-side MOSFET driver circuit.
• VRA: The VRA LDO provides a regulated 5V bias supply for the
current sense circuit and other analog circuitry. It is powered
from the VDDS pin and supplies bias current internally. A
4.7µF filter capacitor is required at the VRA pin.
VDDS
VIN
VDDS
VIN
VDDS
VIN
VR
VRA
VR
VRA
VR
VRA
4.5V VIN 5.5V 5.5V < VIN7.5V 7.5V < VIN14V
FIGURE 14. INPUT SUPPLY CONNECTIONS
• V2P5:The V2P5 LDO provides a regulated 2.5V bias supply for
the main controller circuitry. It is powered from the VRA LDO
and supplies bias current internally. A 10µF filter capacitor is
required at the V2P5 pin.
When the input supply (VDDS) is higher than 7.5V, the VR and
VRA pins should not be connected to any other pins. These pins
should only have a filter capacitor attached. Due to the dropout
voltage associated with the VR and VRA bias regulators, the
VDDS pin must be connected to these pins for designs operating
from a supply below 7.5V. Figure 14 illustrates the required
connections for all cases.
Note: The internal bias regulators, VR and VRA, are not designed
to be outputs for powering other circuitry. Do not attach external
loads to any of these pins. Only the multi-mode pins may be
connected to the V2P5 pin for logic HIGH settings.
High-side Driver Boost Circuit
The gate drive voltage for the high-side MOSFET driver is
generated by a floating bootstrap capacitor, CB (see Figure 10).
When the lower MOSFET (QL) is turned on, the SW node is pulled
to ground and the capacitor is charged from the internal VR bias
regulator through diode DB. When QL turns off and the upper
MOSFET (QH) turns on, the SW node is pulled up to VDDP and the
voltage on the bootstrap capacitor is boosted approximately 6.5V
above VDDP to provide the necessary voltage to power the high-
side driver. An internal Schottky diode is used with CB to help
maximize the high-side drive supply voltage.
Output Voltage Selection
The output voltage may be set to any voltage between 0.6V and
5.0V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification. Using the
pin-strap method, VOUT can be set to one of three standard
voltages as shown in Table 2.
TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS
VSET
LOW
VOUT
1.2V
OPEN
HIGH
1.5V
3.3V
12
FN7730.0
January 23, 2012
Datasheet pdf - http://www.DataSheet4U.net/

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