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PDF ADV3205 Data sheet ( Hoja de datos )
| Número de pieza | ADV3205 | |
| Descripción | 16 X 16 Buffered Analog Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
60 MHz, G = +2, 16 × 16
Buffered Analog Crosspoint Switch
ADV3205
FEATURES
16 × 16 high speed nonblocking switch array
Serial or parallel programming of switch array
Serial data out allows daisy-chaining control of multiple
16 × 16 devices to create larger switch arrays
Complete solution
Buffered inputs
16 output amplifiers
Operates on ±5 V supplies
Low supply current of 50 mA
Excellent video performance, VS = ±5 V
−3 dB bandwidth: 60 MHz
0.1 dB gain flatness: 10 MHz
0.1% differential gain error (RL = 1 kΩ)
0.1° differential phase error (RL = 1 kΩ)
Low all hostile crosstalk: −67 dB at 5 MHz
Output disable allows connection of multiple devices
without loading the output bus
RESET pin allows disabling of all outputs
Power-on reset capability with capacitor to ground
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance
Video routers (NTSC, PAL, S-Video, SECAM)
Video conferencing
CLK
DATA IN
UPDATE
CE
RESET
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
A0
A1
A2
A3
DATA
OUT
80
PARALLEL LATCH
80
DECODE
16 × 5:16 DECODERS
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO “OFF”
16
ADV3205
OUTPUT
256 BUFFER
G = +2
16 INPUTS
SWITCH
MATRIX
16
OUTPUTS
Figure 1.
GENERAL DESCRIPTION
The ADV3205 is a fully buffered crosspoint switch matrix that
operates on ±5 V, making it ideal for video applications. It offers
a −3 dB signal bandwidth of 60 MHz and channel switch times of
less than 60 ns with 0.1% settling. The ADV3205 has excellent
crosstalk performance, and ground/power pins surround all inputs
and outputs to provide extra shielding required for the most
demanding applications. The differential gain and differential
phase of better than 0.1% and 0.1°, respectively, along with 0.1 dB
flatness out to 10 MHz, make the ADV3205 an excellent choice
for many video applications.
The ADV3205 includes 16 independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs.
The ADV3205 has a gain of +2 and operates on voltage supplies
of ±5 V while consuming only 34 mA of current. Channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control, allowing updating of an individual output without
reprogramming the entire array.
The ADV3205 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
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Data Sheet
TIMING CHARACTERISTICS (PARALLEL MODE)
Table 4.
Parameter
Parallel Data Setup Time
Address Setup Time
CLK Enable Width
Parallel Data Hold Time
Address Hold Time
CLK Pulse Separation
CLK-to-UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
ADV3205
Symbol
t1d
t1a
t2
t3d
t3a
t4
t5
t6
Limit
Min Max
20
20
100
20
20
100
0
50
50
100
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
CLK
0
1
A0 TO A3
0
1
D0 TO D4
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t1a
t1d
t4
t3a
t3d
Figure 3. Timing Diagram, Parallel Mode
t5 t6
Table 5. Logic Levels
VIH VIL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
2.0 V min
0.8 V max
VOH
DATA OUT
2.7 V min
VOL
DATA OUT
0.5 V max
IIH
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
20 μA max
IIL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
A3, CE, UPDATE
−400 μA min
IOH
DATA OUT
−400 μA max
IOL
DATA OUT
3.0 mA min
Rev. 0 | Page 5 of 20
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Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.01
1k
+PSRR
–PSRR
0.1 1
FREQUENCY (MHz)
Figure 13. PSRR vs. Frequency
10
100
10
1
0.1
0.1
1 10 100
FREQUENCY (MHz)
Figure 14. Enabled Output Impedance vs. Frequency
1k
0
–20
–40
–60
–80
–100
–120
0.1
1 10
FREQUENCY (MHz)
Figure 15. Off Isolation vs. Frequency, VOUT = 2 V p-p
100
ADV3205
160
140
120
100
80
60
40
20
0
10
10k
100 1k 10k 100k
FREQUENCY (Hz)
Figure 16. Noise vs. Frequency
1M
10M
1k
100
10
1
0.1 1
10 100
FREQUENCY (MHz)
Figure 17. Disabled Output Impedance vs. Frequency
1k
INPUT
OUTPUT
OUTPUT
2
–
INPUT
0 5 10 5 20 25 30 35 40 45 50
5ns/DIV
Figure 18. Settling Time to 0.1%, 2 V Output Step
Rev. 0 | Page 11 of 20
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