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LQ025Q3DW02 Schematic ( PDF Datasheet ) - Sharp

Teilenummer LQ025Q3DW02
Beschreibung Display Module
Hersteller Sharp
Logo Sharp Logo 




Gesamt 29 Seiten
LQ025Q3DW02 Datasheet, Funktion
Technical Document
LCD Specification
LCD Group
LQ025Q3DW02 LCD Module
Product Specification
July 2009
QVGA Normally Black LCD module
featuring very wide viewing angles and
350 nits brightness with 500:1 contrast.






LQ025Q3DW02 Datasheet, Funktion
4. Input Terminal Names and Functions
Recommendation CN [HIROSE] FH26G-67S-0.3SHBW(05)
Pin No. Symbol I/O
Description
1 LED_C (-) -
Power supply for LED (Low voltage)
2 LED_A(+) -
Power supply for LED (High voltage)
3 DGND1 -
Digital Ground
4 NC -
Not connected
5 NC -
Not connected
6 NC -
Not connected
7 NC -
Not connected
8 AGND1 -
Analog Ground
9 VGH -
10 C2P -
Connect to a Stabilizing capacitor
Connect a Booster capacitor to C2N
11 C2N -
Connect a Booster capacitor to C2P
12 C1P -
Connect a Booster capacitor to C1N
13 C1N -
Connect a Booster capacitor to C1P
14 VGL -
15 C3P -
Connect a Stabilizing capacitor to GND
Connect a Booster capacitor to C3N
16 C3N -
Connect a Booster capacitor to C3P
17 AGND2 -
Analog Ground
18 VCIX2 -
19 CYP -
Connect a Stabilizing capacitor to GND
Connect a Booster capacitor to CYN
20 CYN -
Connect a Booster capacitor to CYP
21 VCI -
22 NC -
3.3V(Booster input voltage pin)
Not connected
23 AGND3 -
Analog Ground
24 VCIM -
25 CXP -
Connect a Stabilizing capacitor to GND
Connect a Booster capacitor to CXN
26 CXN -
Connect a Booster capacitor to CXP
27 TEST O
TEST
28 RESB I
System reset
29 DGND2 -
Digital Ground
30 VDDIO -
31 VCORE -
32 DGND3 -
3.3V(Voltage input pin for logic I/O)
Connect a Stabilizing capacitor to GND
Digital Ground
33 DGND4 I
Digital Ground
34 CSB I
Chip select pin of serial interface
35 SDI I
Data input pin in serial mode
36 SCK I
Clock input pin in serial mode
37 VDROP -
38 DEN I
Connect a Stabilizing capacitor
Display enable
39 B5 I
BLUE data signal(MSB)
40 B4 I
BLUE data signal
41 B3 I
BLUE data signal
LD-21704A -3
Remarks
Note 1
Note 1
Note 1
Note 1
Note 3
Note 2
Note 3
Note 2
Note 3
Note 2
Note 3
Note 1
Note 3
Note 2
Note 1
Note 3

6 Page









LQ025Q3DW02 pdf, datenblatt
LD-21704A -9
Note 1)
Driver Output Control (R01h)(POR=0xEFh)
DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W 1 0 0 0 0 1 0 TB RL 1 1 1 0 1 1 1 1
POR
000010xx11101111
Vertical and Horizontal inversion function(TB RL)
Note 2)
Horizontal Porch(R16h)(POR=9F86h)
R/W DC IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W 1 1 0 0 1 1 1 1 1 1 0 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0
POR
1 0 0 1 1 11110 0 0 0 1 1 0
HBP5-0: Set the delay period from falling edge of HSYNC to first valid line.
HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 No. of clock cycle of DOTCLK
000000
2
000001
3
000010
4
000011
5
000100
6
Step = 1
111110
111111
64
65

12 Page





SeitenGesamt 29 Seiten
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