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PDF NL204153AC21-09 Data sheet ( Hoja de datos )
| Número de pieza | NL204153AC21-09 | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL204153AC21-09
54cm (21.3 Type)
QXGA
LVDS interface (4 ports)
PRELIMINARY DATA SHEET
DOD-PP-0442 (2nd edition)
üRoHS
Compliant
2002/95/EC
This PRELIMINARY DATA SHEET is updated
document from DOD-PP-0281(1).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PP-0442 (2nd edition) 1 © NEC LCD Technologies, Ltd.
Published date: January 2008 CP (N)
2007-2008 All rights reserved.
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NL204153AC21-09
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Sub-pixel pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
433.152 (H) × 324.864 (V) mm
54cm (21.3 inches)
a-Si TFT active matrix
16,777,216 colors (8-bit)
2,048 (H) × 1,536 (V) pixels (1 pixel consists of 3 sub-pixels (RGB).)
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.0705 (H) × 0.2115 (V) mm
0.2115 (H) × 0.2115 (V) mm
457.0 (W) × 350.0 (H) × 34.0 (D) mm (typ.)
2,700g (typ.)
750:1 (typ.)
At the contrast ratio ≥ 10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
Viewing angle with optimum grayscale (γ=DICOM): normal axis
(perpendicular)
Antiglare
2H (min.) [by JIS K5400]
At LCD panel center
72 % (typ.) [against NTSC color space]
Ton+Toff (10%←→ 90%)
24ms (typ.)
Note1
At the maximum luminance control
800cd/m2 (typ.)
4 ports LVDS interface (THC63LVD824×2pcs, THine Electronics, Inc. or
equivalent)
[RGB 8-bit signals, Data enable signal (DE), Dot clock (CK)]
LCD panel signal processing board: 12.0V
Inverter: 24.0V
Direct light type: 16 cold cathode fluorescent lamps with an inverter
2
2
2
Backlight
Replaceable part
• Inverter: 213PW071
2
Power consumption
At checkered flag pattern, the maximum luminance control
73.2W (typ.)
Note1: When the product luminance is 400cd/m2, the gamma characteristic is designed to γ=DICOM.
2
PRELIMINARY DATA SHEET DOD-PP-0422 (2nd edition)
5
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NL204153AC21-09
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VDD
Note1
10.8V
0V
ON
0.1ms < Tr < 80ms
OFF
9.6V 10.8V
VDD dip < 20ms
LVDS signals *1,*2
Note2
0V
VALID period
ON
10.8V
Toff > 200ms
10ms < t < 35ms
10ms < t < 35ms
0ms < t < 35ms
*1: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-, CKB+/-,
DC0+/-, DC1+/-, DC2+/-, DC3+/-, CKC+/-, DD0+/-, DD1+/-, DD2+/-, DD3+/-, CKD+/-
*2: LVDS signals should be measured at the terminal of 100 Ω resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a protection
circuit may work, and then this product may not work.
Note2: LVDS signals must be Low or High-impedance, exclude the VALID period (See above
sequence diagram), in order to avoid that internal circuits is damaged.
If some of signals are cut while this product is working, even if the signal input to it once again,
it might not work normally. VDD should be cut when the display and function signals are
stopped.
Note3: The backlight should be turned on within the valid period of LVDS signals, in order to avoid
unstable data display.
4.4.2 Inverter
Voltage
24.0V
22.8V
tr ≤ 800ms
BRTC
VDDB
0V
0ms<t
Time
0ms<t
2
2
2
Note1: The backlight should be turned on within the valid period of LVDS signals, in order to avoid
unstable data display.
Note2: If tr is more than 800ms, the backlight will be turned off by a protection circuit for inverter.
Note3: When VDDB is ON and BRTC is high, voltage to BRTI, BRTP and PWSEL terminals should
be applied.
PRELIMINARY DATA SHEET DOD-PP-0422 (2nd edition)
11
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