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PDF SST38VF6402 Data sheet ( Hoja de datos )
| Número de pieza | SST38VF6402 | |
| Descripción | (SST38VF6401 - SST38VF6404) 64Mbit(x16) Advanced Multi-Purpose Flash Plus | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
FEATURES:
SST38VF640x2.7V 64Mb (x16) MPF+ memories
Preliminary Specification
• Organized as 4M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: up to 100,000 Cycles minimum
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 4 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• 128-bit Unique ID
• Security-ID Feature
– 256 Word, user One-Time-Programmable
• Protection and Security Features
– Hardware Boot Block Protection/WP# Input Pin,
Uniform (32 KWord) and Non-Uniform (8 KWord)
options available
– User-controlled individual block (32 KWord) pro-
tection, using software only methods
– Password protection
• Hardware Reset Pin (RST#)
• Fast Read and Page Read Access Times:
– 90 ns Read access time
– 25 ns Page Read access times
- 4-Word Page Read buffer
• Latched Address and Data
• Fast Erase Times:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
• Erase-Suspend/-Resume Capabilities
• Fast Word and Write-Buffer Programming
Times:
– Word-Program Time: 7 µs (typical)
– Write Buffer Programming Time: 1.75 µs / Word
(typical)
- 16-Word Write Buffer
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– RY/BY# Output
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• CFI Compliant
• Packages Available
– 48-lead TSOP
– 48-ball TFBGA
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST38VF6401, SST38VF6402, SST38VF6403, and
SST38VF6404 devices are 4M x16 CMOS Advanced
Multi-Purpose Flash Plus (Advanced MPF+) manufactured
with SST proprietary, high-performance CMOS Super-
Flash technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufacturabil-
ity compared with alternate approaches. The
SST38VF6401/6402/6403/6404 write (Program or Erase)
with a 2.7-3.6V power supply. These devices conform to
JEDEC standard pin assignments for x16 memories.
Featuring high performance Word-Program, the
SST38VF6401/6402/6403/6404 provide a typical Word-
Program time of 7 µsec. For faster word-programming per-
formance, the Write-Buffer Programming feature, has a typ-
ical word-program time of 1.75 µsec. These devices use
Toggle Bit or Data# Polling to indicate Program operation
completion. In addition to single-word Read, Advanced
MPF+ devices provide a Page-Read feature that enables a
faster word read time of 25 ns, for words on the same page.
To protect against inadvertent write, the SST38VF6401/
6402/6403/6404 have on-chip hardware and Software
Data Protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, these devices
are available with up to 100,000 cycles minimum endur-
ance. Data retention is rated at greater than 100 years.
The SST38VF6401/6402/6403/6404 are suited for applica-
tions that require the convenient and economical updating
of program, configuration, or data memory. For all system
applications, Advanced MPF+ significantly improve perfor-
mance and reliability, while lowering power consumption.
These devices inherently use less energy during Erase and
Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. For any given voltage range,
the SuperFlash technology uses less current to program
and has a shorter erase time; therefore, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies.
©2008 Silicon Storage Technology, Inc.
S71309-03-000
08/08
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Preliminary Specification
The SST38VF6401/6402/6403/6404 also provide a RY/
BY# signal. This signal indicates the status of a Program or
Erase operation.
If a Program or Erase operation is attempted on a pro-
tected sector or block, the operation will abort. After the
device initiates an abort, the corresponding Write Opera-
tion Status Detection Bits will stay active for approximately
200ns (program or erase) before the device returns to read
mode.
For the status of these bits during a Write operation, see
Table 1.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit
(DQ6) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ6 will be set to ‘1’ if a Read operation is attempted
on an Erase-Suspended Sector or Block. If Program oper-
ation is initiated in a sector/block not selected in Erase-Sus-
pend mode, DQ6 will toggle.
Data# Polling (DQ7)
When the SST38VF6401/6402/6403/6404 are in an inter-
nal Program operation, any attempt to read DQ7 will pro-
duce the complement of true data. For a Program Buffer-
to-Flash operation, DQ7 is the complement of the last
word loaded in the Write-Buffer using the Write-to-Buffer
command. Once the Program operation is completed,
DQ7 will produce valid data. Note that even though DQ7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid. Valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs.
During an internal Erase operation, any attempt to read
DQ7 will produce a ‘0’. Once the internal Erase operation
is completed, DQ7 will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 11 for Data# Polling timing dia-
gram and Figure 26 for a flowchart.
TABLE 1: Write Operation Status
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector or block is being actively erased or erase-sus-
pended. Table 1 shows detailed bit status information. The
Toggle Bit (DQ2) is valid after the rising edge of the last
WE# (or CE#) pulse of Write operation. See Figure 12 for
Toggle Bit timing diagram and Figure 26 for a flowchart.
DQ1
If an operation aborts during a Write-to-Buffer or Program
Buffer-to-Flash operation, DQ1 is set to ‘1’. To reset DQ1 to
‘0’, issue the Write-to-Buffer Abort Reset command to exit
the abort state. A power-off/power-on cycle or a Hardware
Reset (RST# = 0) will also clear DQ1.
RY/BY#
The RY/BY# pin can be used to determine the status of a
Program or Erase operation. The RY/BY# pin is valid after
the rising edge of the final WE# pulse in the command
sequence. If RY/BY# = 0, then the device is actively pro-
gramming or erasing. If RY/BY# = 1, the device is in Read
mode. The RY/BY# pin is an open drain output pin. This
means several RY/BY# can be tied together with a pull-up
resistor to VDD..
Status
Normal
Operation
Standard Program
Standard Erase
DQ71
DQ7#
0
DQ6
Toggle
Toggle
DQ21
No Toggle
Toggle
DQ1
0
N/A
RY/BY#2
0
0
Erase-Suspend Read from Erase-Suspended 1
Mode
Sector/Block
No toggle Toggle
N/A
1
Read from Non- Erase-
Suspended Sector/Block
Data
Data
Data
Data
1
Program
DQ7# Toggle
N/A
N/A
0
Program Buffer- Busy
to-Flash
Abort
DQ7#3
DQ7#3
Toggle
Toggle
N/A
N/A
0
1
0
0
T1.0 1309
1. DQ7 and DQ2 require a valid address when reading status information.
2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode.
3. During a Program Buffer-to-Flash operation, the datum on the DQ7 pin is the complement of DQ7 of the last word loaded in the Write-
Buffer using the Write-to-Buffer command.
©2008 Silicon Storage Technology, Inc.
5
S71309-03-000
08/08
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
FUNCTIONAL BLOCK DIAGRAM
Preliminary Specification
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer & Latches
CE#
OE#
WE#
WP#
RESET#
Control Logic
FIGURE 1: Functional Block Diagram
Y-Decoder
I/O Buffers and Data Latches
DQ15 - DQ0
RY/BY#
1309 B1.1
©2008 Silicon Storage Technology, Inc.
11
S71309-03-000
08/08
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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| PDF Descargar | [ Datasheet SST38VF6402.PDF ] | |
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