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Teilenummer | SH-1 |
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Beschreibung | (SH-1 / SH-2) 32-Bit RISC Microcomputer | |
Hersteller | Renesas Technology | |
Logo |   | |
Gesamt 70 Seiten www.DataSheet.co.kr
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr
Rev. 5.00 Jun 30, 2004 page iv of xiv
REJ09B0171-0500O
Datasheet pdf - http://www.DataSheet4U.net/
6 Page www.DataSheet.co.kr
6.1.23 EXTS (Extend as Signed): Arithmetic Instruction............................................... 171
6.1.24 EXTU (Extend as Unsigned): Arithmetic Instruction.......................................... 173
6.1.25 JMP (Jump): Branch Instruction .......................................................................... 174
6.1.26 JSR (Jump to Subroutine): Branch Instruction (Class: Delayed Branch
Instruction)........................................................................................................... 175
6.1.27 LDC (Load to Control Register): System Control Instruction (Class: Interrupt
Disabled Instruction)............................................................................................ 177
6.1.28 LDRE (Load Effective Address to RE Register): System Control Instruction .... 180
6.1.29 LDRS (Load Effective Address to RS Register): System Control Instruction..... 182
6.1.30 LDS (Load to System Register): System Control Instruction.............................. 184
6.1.31 MAC.L (Multiply and Accumulate Calculation Long): Arithmetic Instruction .. 189
6.1.32 MAC.W (Multiply and Accumulate Calculation Word): Arithmetic Instruction 193
6.1.33 MOV (Move Data): Data Transfer Instruction .................................................... 196
6.1.34 MOV (Move Immediate Data): Data Transfer Instruction .................................. 202
6.1.35 MOV (Move Peripheral Data): Data Transfer Instruction ................................... 205
6.1.36 MOV (Move Structure Data): Data Transfer Instruction..................................... 209
6.1.37 MOVA (Move Effective Address): Data Transfer Instruction ............................ 213
6.1.38 MOVT (Move T Bit): Data Transfer Instruction ................................................. 215
6.1.39 MUL.L (Multiply Long): Arithmetic Instruction................................................. 216
6.1.40 MULS.W (Multiply as Signed Word): Arithmetic Instruction ............................ 217
6.1.41 MULU.W (Multiply as Unsigned Word): Arithmetic Instruction ....................... 218
6.1.42 NEG (Negate): Arithmetic Instruction................................................................. 219
6.1.43 NEGC (Negate with Carry): Arithmetic Instruction ............................................ 220
6.1.44 NOP (No Operation): System Control Instruction............................................... 221
6.1.45 NOT (NOT—Logical Complement): Logic Operation Instruction ..................... 222
6.1.46 OR (OR Logical) Logic Operation Instruction .................................................... 223
6.1.47 ROTCL (Rotate with Carry Left): Shift Instruction............................................. 225
6.1.48 ROTCR (Rotate with Carry Right): Shift Instruction .......................................... 226
6.1.49 ROTL (Rotate Left): Shift Instruction ................................................................. 227
6.1.50 ROTR (Rotate Right): Shift Instruction............................................................... 228
6.1.51 RTE (Return from Exception): System Control Instruction ................................ 229
6.1.52 RTS (Return from Subroutine): Branch Instruction (Class: Delayed Branch
Instruction)........................................................................................................... 231
6.1.53 SETRC (Set Repeat Count to RC): System Control Instruction .......................... 233
6.1.54 SETT (Set T Bit): System Control Instruction..................................................... 235
6.1.55 SHAL (Shift Arithmetic Left): Shift Instruction.................................................. 236
6.1.56 SHAR (Shift Arithmetic Right): Shift Instruction ............................................... 237
6.1.57 SHLL (Shift Logical Left): Shift Instruction ....................................................... 238
6.1.58 SHLLn (Shift Logical Left n Bits): Shift Instruction........................................... 239
6.1.59 SHLR (Shift Logical Right): Shift Instruction..................................................... 241
Rev. 5.00 Jun 30, 2004 page x of xiv
REJ09B0171-0500O
Datasheet pdf - http://www.DataSheet4U.net/
12 Page | ||
Seiten | Gesamt 70 Seiten | |
PDF Download | [ SH-1 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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