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XQR2V3000 Schematic ( PDF Datasheet ) - Xilinx

Teilenummer XQR2V3000
Beschreibung QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
Hersteller Xilinx
Logo Xilinx Logo 




Gesamt 70 Seiten
XQR2V3000 Datasheet, Funktion
www.DataSheet.co.kr
0
R QPro Virtex-II 1.5V Radiation
Hardened QML Platform FPGAs
DS124 (v1.1) January 8, 2004
0 0 Product Specification
Summary of Radiation Hardened QPro™ Virtex™-II Features
• Industry First Radiation Hardened Platform FPGA
Solution
• Guaranteed total ionizing dose to 200K Rad(si)
• Latch-up immune to LET > 160 MeV-cm2/mg
• SEU in GEO upsets < 1.5E-6 per device day
achievable with recommended redundancy
implementation
• Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
• Guaranteed over the full military temperature range
(–55° C to +125° C)
• Ceramic and Plastic Wire-Bond and Flip-Chip Grid
Array Packages
• IP-Immersion Architecture
- Densities from 1M to 6M system gates
- 300+ MHz internal clock speed (Advance Data)
- 622+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
- 2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
- Up to 1 Mb of distributed SelectRAM resources
• High-Performance Interfaces to External Memory
- DRAM interfaces
· SDR/DDR SDRAM
· Network FCRAM
· Reduced Latency DRAM
- SRAM interfaces
· SDR/DDR SRAM
· QDR SRAM
- CAM interfaces
• Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
• Flexible Logic Resources
- Up to 67,584 internal registers/latches with Clock
Enable
- Up to 67,584 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and sum-of-products
support
- Internal 3-state busing
• High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
· Precise clock de-skew
· Flexible frequency synthesis
· High-resolution phase shifting
- 16 global clock multiplexer buffers
• Active Interconnect Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
• SelectIO™-Ultra Technology
- Up to 824 user I/Os
- 19 single-ended and six differential standards
- Programmable sink current (2 mA to 24 mA) per
I/O
- Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- Differential Signaling
· 622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
· Bus LVDS I/O
· Lightning Data Transport (LDT) I/O with current
driver buffers
· Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
· Built-in DDR input and output registers
- Proprietary high-performance SelectLink
Technology
· High-bandwidth data path
· Double Data Rate (DDR) link
· Web-based HDL generation methodology
• Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
• SRAM-Based In-System Configuration
- Fast SelectMAP configuration
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
- Readback capability
• 0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V
VCCAUX Auxiliary and VCCO I/O Power Supplies
• IEEE 1149.1 Compatible Boundary-Scan Logic Support
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS124 (v1.1) January 8, 2004
Product Specification
www.xilinx.com
1-800-255-7778
1
Datasheet pdf - http://www.DataSheet4U.net/






XQR2V3000 Datasheet, Funktion
www.DataSheet.co.kr
QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
R
Virtex-II Ordering Information
Example:
Device Type
Speed Grade(1)
XQR2V3000 -4 CG 717 V
Product Grade
Number of Pins
Package Type
Device Ordering Options
Device Type
Package
Product Manufacturing
Grade
Flow(2)
Temperature
Range
XQR2V1000
XQR2V3000
XQR2V6000
FG456
BG575
BG728
456-ball Plastic Fine Pitch BGA Package
575-ball Plastic BGA Package
728-ball Plastic BGA Package
M
M-Grade
Military Ceramic
V QPRO-PLUS TC = 55° C to
H QPRO-FCC +125° C
CG717
CF1144
717-column Hermetic Ceramic CGA
Package
1144-column Non-hermetic Ceramic
Flip-Chip Package
N
Class N
Military Plastic
TJ = 55° C to
R QPRO+PLUS +125° C
PEM
Notes:
1. -4 is the only supported speed grade.
2. A detailed explanation of the Manufacturing and Test Flows is available at http://www.xilinx.com/products/milaero/rpt003.pdf
Valid Ordering Combinations
Grade
XQR2V1000
XQR2V3000
XQR2V6000
N
XQR2V1000-4FG456N
XQR2V3000-4BG728N
XQR2V1000-4BG575N
R
XQR2V1000-4FG456R
XQR2V3000-4BG728R
XQR2V1000-4BG575R
M XQR2V3000-4CG717M XQR2V6000-4CF1144M1
V XQR2V3000-4CG717V
H
Notes:
1. CF1144 is non-Hermetic Ceramic.
XQR2V6000-4CF1144H1
6
www.xilinx.com
DS124 (v1.1) January 8, 2004
1-800-255-7778
Product Specification
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









XQR2V3000 pdf, datenblatt
www.DataSheet.co.kr
QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
R
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in Figure 8 and Figure 9. Each
bank has multiple VCCO pins, all of which must be con-
nected to the same voltage. This voltage is determined by
the output standards in use.
Bank 0
Bank 1
Bank 5
Bank 4
ug002_c2_014_112900
Figure 8: Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS, FG, & BG)
Some input standards require a user-supplied threshold
voltage (VREF), and certain user-I/O pins are automatically
configured as VREF inputs. Approximately one in six of the
I/O pins in the bank assume this role.
Bank 1
Bank 0
Bank 4
Bank 5
ds031_66_112900
Figure 9: Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
VREF pins within a bank are interconnected internally, and
consequently only one VREF voltage can be used within
each bank. However, for correct operation, all VREF pins in
the bank must be connected to the external reference volt-
age source.
The VCCO and the VREF pins for each bank appear in the
device pinout tables. Within a given package, the number of
VREF and VCCO pins can vary depending on the size of
device. In larger devices, more I/O pins convert to VREF
pins. Since these are always a superset of the VREF pins
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All VREF pins for the largest device anticipated must be con-
nected to the VREF voltage and are not used for I/O. In
smaller devices, some VCCO pins used in larger devices do
not connect within the package. These unconnected pins
can be left unconnected externally, or, if necessary, they can
be connected to VCCO to permit migration to a larger device.
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bidirectional standards in the same bank:
1. Combining output standards only. Output standards
with the same output VCCO requirement can be
combined in the same bank.
Compatible example:
SSTL2_I and LVDS_25_DCI outputs
Incompatible example:
SSTL2_I (output VCCO = 2.5V) and
LVCMOS33 (output VCCO = 3.3V) outputs
2. Combining input standards only. Input standards
with the same input VCCO and input VREF requirements
can be combined in the same bank.
Compatible example:
LVCMOS15 and HSTL_IV inputs
Incompatible example:
LVCMOS15 (input VCCO = 1.5V) and
LVCMOS18 (input VCCO = 1.8V) inputs
Incompatible example:
HSTL_I_DCI_18 (VREF = 0.9V) and
HSTL_IV_DCI_18 (VREF = 1.1V) inputs
3. Combining input standards and output standards.
Input standards and output standards with the same
input VCCO and output VCCO requirement can be
combined in the same bank.
Compatible example:
LVDS_25 output and HSTL_I input
Incompatible example:
LVDS_25 output (output VCCO = 2.5V) and
HSTL_I_DCI_18 input (input VCCO = 1.8V)
4. Combining bidirectional standards with input or
output standards. When combining bidirectional I/O
with other standards, make sure the bidirectional
standard can meet rules 1 through 3 above.
5. Additional rules for combining DCI I/O standards.
a. No more than one Single Termination type (input or
output) is allowed in the same bank.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
b. No more than one Split Termination type (input or
output) is allowed in the same bank.
12
www.xilinx.com
DS124 (v1.1) January 8, 2004
1-800-255-7778
Product Specification
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





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