PDF QS5917T Data sheet ( Hoja de datos )

Número de pieza	QS5917T
Descripción	LOW SKEW CMOS PLL CLOCK DRIVER
Fabricantes	Integrated Device Technology
Logotipo
Hay una vista previa y un enlace de descarga de QS5917T (archivo pdf) en la parte inferior de esta página. Total 7 Páginas
No Preview Available ! www.DataSheet.co.kr QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIALTEMPERATURERANGE QS5917T FEATURES: • 5V operation • 2xQ output, Q/2 output, Q output • Outputs tri-state while RST low • Internal loop filter RC network • Low noise TTL level outputs • < 500ps output skew, Q0-Q4 • PLL disable feature for low frequency testing • Balanced Drive Outputs ± 24mA • 132MHz maximum frequency (2xQ output) • Functional equivalent to Motorola MC88915 • ESD > 2000V • Latch-up > –300mA • Available in QSOP and PLCC packages FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteris- tics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feed- back and a divide-by-2 in the VCO path allow applications to be custom- ized for linear VCO operation over a wide range of input SYNC fre- quencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5917T is designed for use in high-performance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distri- bution networks. For more information on PLL clock driver products, see Application Note AN-227. RST SYNC0 SYNC1 REF_SEL 0 1 LOCK FEEDBACK PHASE DETECTOR LOOP FILTER VCO PLL_EN FREQ_SEL 01 1 /2 0 RDRDRDRDRDRDRD Q Q Q Q Q Q QQ Q/2 Q5 Q4 Q3 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 2000 Integrated Device Technology, Inc. 1 Q2 Q1 Q0 2xQ JULY 2000 DSC-5227/2 Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIALTEMPERATURERANGE INPUT TIMING REQUIREMENTS Symbol Description Min. Max. Unit tR, tF Maximum input rise and fall times, 0.8V to 2V FI Input Clock Frequency, SYNC0, SYNC1 (1) tPWC Input clock pulse, HIGH or LOW DH Duty cycle, SYNC0, SYNC1 — 3 ns 14 F2XQ MHz 2 — ns 25 75 % NOTE: 1. The FI specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations. SWITCHING CHARACTERISTICS(1) Symbol tSKR tSKF tSKALL tPW tPW tJ tPD tPD tLOCK tPZH tPZL tPHZ tPLZ tR, tF Parameter Output Skew Between Rising Edges, Q0-Q4 and Q/2 (1) Output Skew Between Falling Edges, Q0-Q4 (1) Output Skew, All Outputs (1) Pulse Width, Q5, 2xQ outputs Pulse Width, Q0-Q4, Q/2 outputs (1) Cycle-to-Cycle Jitter, 33MHz (3) SYNC Input to Feedback Delay, 28MHz SYNC Input to Feedback Delay, 33MHz, 50Ω to 1.5V SYNC to Phase Lock Output Enable Time, RST LOW to HIGH (2) Output Disable Time, RST HIGH to LOW (2) Output Rise/Fall Times, 0.8V to 2V Min. — — — TCY/2 − 0.65 TCY/2 − 0.5 — − 100 − 100 — 0 0 0.4 Max. 350 350 500 TCY/2 + 0.65 TCY/2 + 0.5 0.25 400 400 10 7 6 1.5 Unit ps ps ps ns ns ns ps ps ms ns ns ns NOTES: 1. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). 2. Measured in open loop mode PLL_EN = 0. 3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input frequencies. 5 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page

Páginas	Total 7 Páginas
PDF Descargar	[ Datasheet QS5917T.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
QS5917T	LOW SKEW CMOS PLL CLOCK DRIVER	Integrated Device Technology

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar