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ADV7401 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV7401
Beschreibung Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 21 Seiten
ADV7401 Datasheet, Funktion
10-Bit, Integrated, Multiformat SDTV/HDTV
Video Decoder and RGB Graphics Digitizer
ADV7401
FEATURES
Four 10-bit ADCs sampling up to 140 MHz
(140 MHz speed grade only)
12 analog input channel mux
SCART fast blank support
Internal antialias filters
NTSC/PAL/SECAM color standards support
525p-/625p-component progressive scan support
720p-/1080i-component HDTV support
Digitizes RGB graphics up to 1280 × 1024 @ 75 Hz (SXGA)
(140 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI Rx IC
Any-to-any, 3 × 3 color-space conversion matrix
Industrial temperature range (−40°C to +85°C)
12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface
Programmable interrupt request output pin
VBI data slicer (including teletext)
APPLICATIONS
LCD/DLP™ rear projection HDTVs
PDP HDTVs
CRT HDTVs
LCD/DLP front projectors
LCD TV (HDTV ready)
HDTV STBs with PVR
Hard-disk-based video recorders
Multiformat scan converters
DVD recorders with progressive scan input support
AVR receiver
GENERAL DESCRIPTION
The ADV7401 is a high quality, single chip, multiformat video
decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-video into a digital ITU-R BT.656
format. The ADV7401 also supports the decoding of a
component RGB/YPrPb video signal into a digital YCrCb or
RGB pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
1250i, and many other HD and SMPTE standards. Graphic
digitization is also supported by the ADV7401; it is capable of
digitizing RGB graphics signals from VGA to SXGA rates and
converting them into a digital RGB or YCrCb pixel output
stream. SCART and overlay functionality are enabled by the
ADV7401’s ability to simultaneously process CVBS and
standard definition RGB signals. The mixing of these signals is
controlled by the fast blank pin.
The ADV7401 contains two main processing sections. The first
is the standard definition processor (SDP), which processes all
PAL, NTSC, and SECAM signal types. The second is the
component processor (CP), which processes YPrPb and RGB
component formats, including RGB graphics. For more specific
descriptions of the ADV7401 features, see the Detailed
Functionality and Detailed Description sections.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.






ADV7401 Datasheet, Funktion
ADV7401
3 All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00.
4 All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.
5 Max INL and DNL specifications obtained with part configured for component video input.
6 Specification for ADV7401BSTZ-110 and ADV7401KSTZ-140 only.
7 Specification for ADV7401KSTZ-140 only.
8 Guaranteed by characterization.
9 To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIH on Pin 38 = 1.2 V.
10 To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIL on Pin 38 = 0.4 V.
11 Pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 79, 83, 84, 87, 88, 95, 96, 97, 100.
12 VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
13 Pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45.
14 Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1 and ADC2 powered up only, for SCART FB, all ADCs powered up.
Rev. B | Page 5 of 20

6 Page









ADV7401 pdf, datenblatt
Pin No.
4
99
98
81, 19
82, 16
80
78
36
38
37
46
70
59
15
64
65
61, 62
68, 69
67
86
85
79
35
52
77
Mnemonic
HS/CS
VS
FIELD/DE
SDA1, SDA2
SCLK1, SCLK2
ALSB
RESET
LLC1
XTAL
XTAL1
ELPF
TEST0
TEST1
SFL/SYNC_OUT
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
BIAS
HS_IN/CS_IN
VS_IN
DE_IN
DCLK_IN
SOG
SOY
ADV7401
Type
O
O
O
I/O
I
I
I
O
I
O
O
NC
O
O
O
O
I
I
O
I
I
I
I
I
I
Function
HS is a Horizontal Synchronization Output Signal (SDP and CP modes).
CS is a Digital Composite Synchronization Signal (and can be selected
while in CP mode).
Vertical Synchronization Output Signal (SDP and CP modes).
Field Synchronization Output Signal (all interlaced video modes). This
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow
direct connection to a HDMI/DVI Tx IC.
I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the
control port and SDA2 is the data line for the VBI readback port.
I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock
line for the control port and SCLK2 is the clock line for the VBI data
readback port.
This pin selects the I2C address for the ADV7401 control and VBI
readback ports. ALSB set to Logic 0 sets the address for a write to control
port of 0x40 and the readback address for the VBI port of 0x21. ALSB set
to a logic high sets the address for a write to control port of 0x42 and the
readback address for the VBI port of 0x23.
System Reset Input, Active Low. A minimum low reset pulse width of 5
ms is required to reset the ADV7401 circuitry.
LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz
to 140 MHz for ADV7401KSTZ-140; 12.825 MHz to 110 MHz for
ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80).
Input pin for 28.63636 MHz crystal, or can be overdriven by an external
3.3 V 28.63636 MHz clock oscillator source to clock the ADV7401.
This pin should be connected to the 28.63636 MHz crystal or left as a no
connect if an external 3.3 V 28.63636 MHz clock oscillator source is used
to clock the ADV7401. In crystal mode, the crystal must be a
fundamental crystal.
The recommend external loop filter must be connected to this ELPF pin.
This pin should be left unconnected or alternatively tied to AGND.
This pin should be left unconnected.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream
which can be used to lock the subcarrier frequency when this decoder is
connected to any Analog Devices digital video encoder. SYNC_OUT is
the sliced sync output signal available only in CP mode.
Internal Voltage Reference Output.
Common-Mode Level Pin (CML) for the internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ)
between pin and ground.
Can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB
mode.
VS Input Signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI Rx IC).
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS
input mode.
Sync on Green Input. Used in embedded sync mode.
Sync on Luma Input. Used in embedded sync mode.
Rev. B | Page 11 of 20

12 Page





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