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PDF LQ106K1LA03 Data sheet ( Hoja de datos )

Número de pieza LQ106K1LA03
Descripción LCD Module
Fabricantes Sharp 
Logotipo Sharp Logotipo



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LQ106K1LA03 pdf
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LD- 18714A-3
1. Application
This technical literature applies to a color TFT-LCD module, LQ106K1LA03.
2. Overview
This module is a color active matrix LCD module incorporating amorphous silicon TFT (Thin Film Transistor). It is
composed of a color TFT-LCD panel, driver ICs, control circuit and power supply circuit and a backlight unit. Graphics
and texts can be displayed on a 1280×3×768 dots panel with 262,144 colors by using LVDS (Low Voltage Differential
Signaling) to interface and supplying +3.3V DC supply voltage for TFT-LCD panel driving and supply voltage for
backlight.
In this TFT-LCD panel , low reflection / color filters of excellent color performance and backlights of high brightness
are incorporated to realize brighter and clearer pictures, making this model optimum for use in multi-media applications.
Optimum viewing direction is 6 o'clock.
White-LED Backlight-driving DC/DC converter is not built in this module.
3. Mechanical Specifications
Parameter
Display size
Active area
Pixel format
Aspect ratio
Pixel pitch
Pixel configuration
Display mode
Surface treatment
Specifications
27 (10.6") Diagonal
230.4(H)×138.2 (V)
1280 (H)×768 (V)
(1 pixel = R+G+B dots)
15 : 9
0.180 (H)×0.180 (V)
R,G,B vertical stripe
Normally white
Glare and hard-coating 2H
Low reflection
Unit
cm
mm
pixel
mm
Parameter
Min.
Unit outline dimensions
[Note 1]
Width
Height
Depth
250.1
151.5
Mass
[Note 1] Excluding the projection part.
Outline dimensions is shown in Fig.2
Typ.
250.6
152.0
175
Max.
251.1
152.5
5.0
190
Unit
mm
mm
mm
g
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LQ106K1LA03 arduino
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6-3. LVDS input specification
6-3-1. AC characteristics
Parameter
Input Data Position 0 (tRCIP=15.38ns)
Input Data Position 1 (tRCIP=15.38ns)
Input Data Position 2 (tRCIP=15.38ns)
Input Data Position 3 (tRCIP=15.38ns)
Input Data Position 4 (tRCIP=15.38ns)
Input Data Position 5 (tRCIP=15.38ns)
Input Data Position 6 (tRCIP=15.38ns)
Phase Lock Loop Set
Input Clock Period
LVDS input timing
tRIP2
tRIP3
tRIP4
tRIP5
tRIP6
tRIP0
tRIP1
LD- 18714A-9
Symbol
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
tRPLL
tRCIP
Vcc=+3.0V +3.6V
Min Typ.
-0.25
0.0
tRCIP/7-0.25
2 tRCIP/7-0.25
3 tRCIP/7-0.25
4 tRCIP/7-0.25
tRCIP/7
2 tRCIP/7
3 tRCIP/7
4 tRCIP/7
5 tRCIP/7-0.25 5 tRCIP/7
6 tRCIP/7-0.25 6 tRCIP/7
14.9 15.4
Ta 0 +50
Max.
+0.25
tRCIP/7+0.25
2 tRCIP/7+0.25
3 tRCIP/7+0.25
4 tRCIP/7+0.25
5 tRCIP/7+0.25
6 tRCIP/7+0.25
10
20
Unit
ns
ns
ns
ns
ns
ns
ns
ms
ns
RxINi+/-
RxINi6 RxINi5 RxINi4 RxINi3 RxINi2 RxINi1 RxINi0 RxINi6 RxINi5 RxINi4 RxINi3 RxINi2 RxINi1
CK IN+/-
i=0,1,2
LVDS phase lock loop set
VCC
CK IN+/-
3.0V
PLLCLK
6-3-2.LVDS data
CK IN+/-
Previous Cycle
Vdiff=0
tRCIP
Vdiff=0
Note
Vdiff=(RxINi+)-(RxINi-) (CK IN+)-(CK IN-)
Vdiff=0V
tRPLL
2.0V
Current Cycle
RxIN0+/-
RxIN1+/-
RxIN2+/-
R4’ R3’ R2’ R1’ R0’ G0 R5 R4 R3 R2 R1 R0 G0”
G5’ G4’ G3’ G2’ G1’ B1 B0 G5 G4 G3 G2 G1 B1”
HSYNC B5’ B4’ B3’ B2’ ENAB HSYNC VSYNC B5 B4 B3 B2 ENAB”
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