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PDF CY14V104NA Data sheet ( Hoja de datos )
| Número de pieza | CY14V104NA | |
| Descripción | 4-Mbit (512 K x 8 / 256 K x 16) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY14V104LA
CY14V104NA
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Features
Functional Description
■ 25 ns and 45 ns access times
■ Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16
(CY14V104NA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1-million STORE cycles to QuantumTrap
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
■ 20 year data retention
■ Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram [1, 2, 3]
Quatrum Trap
VCC VCCQ VCAP
2048 X 2048
A0 R
POWER
A1 O
STORE
CONTROL
A2
A3
A4
A5
W
RECALL
D
E STATIC RAM
STORE/RECALL
CONTROL
HSB
A6 C ARRAY
A7
A8
A17
O 2048 X 2048
D
E
SOFTWARE
DETECT
A14 - A2
A18 R
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A9 A10 A11 A12 A13 A14 A15 A16
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-53954 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 6, 2011
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1 page  
CY14V104LA
CY14V104NA
During any STORE operation, regardless of how it is initiated,
the CY14V104LA/CY14V104NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14V104LA/CY14V104NA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Data is transferred from SRAM to the non-volatile memory by a
software address sequence. The CY14V104LA/CY14V104NA
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from non-volatile memory to the SRAM by a
software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Table 1. Mode Selection
CE WE
HX
LH
LL
LH
OE
BHE, BLE[5]
A15–A0[6]
Mode
I/O
Power
X X X Not Selected Output High Z Standby
L
L
X
Read SRAM Output Data
Active
X
L
X
Write SRAM Input Data
Active
L
X
0x4E38
Read SRAM Output Data
Active[7]
0xB1C7
Read SRAM Output Data
0x83E0
Read SRAM Output Data
0x7C1F
Read SRAM Output Data
0x703F
Read SRAM Output Data
0x8B45
AutoStore Output Data
Disable
Notes
5. BHE and BLE are applicable for × 16 configuration only.
6.
While there are
modes. Rest of
19 address lines on the CY14V104LA
the address lines are don’t care.
(18
address
lines
on
the
CY14V104NA),
only
the
13
address
lines
(A14–A2)
are
used
to
control
software
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53954 Rev. *F
Page 5 of 22
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5 Page 
CY14V104LA
CY14V104NA
AC Switching Characteristics
Over the Operating Range
Parameters [13]
Cypress
Parameter
Alt Parameter
Description
SRAM Read Cycle
tACE
tRC[14]
tAA[15]
tACS
tRC
tAA
tDOE
tOHA[15]
tLZCE[16, 17]
tHZCE[16, 17]
tLZOE[16, 17]
tHZOE[16, 17]
tPU[16]
tPD[16]
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
tDBE
tLZBE[16]
tHZBE[16]
–
–
–
SRAM Write Cycle
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
tWC tWC
tPWE
tWP
tSCE
tCW
tSD tDW
tHD tDH
tAW tAW
tSA tAS
tHA tWR
tHZWE[16, 17, 18] tWZ
tLZWE[16, 17]
tOW
tBW –
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
25 ns
Min Max
– 25
25 –
– 25
– 12
3–
3–
– 10
0–
– 10
0–
– 25
– 12
0–
– 10
25 –
20 –
20 –
10 –
0–
20 –
0–
0–
– 10
3–
20 –
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [14, 15, 19]
tRC
Address
Address Valid
tAA
45 ns
Min Max
– 45
45 –
– 45
– 20
3–
3–
– 15
0–
– 15
0–
– 45
– 20
0–
– 15
45 –
30 –
30 –
15 –
0–
30 –
0–
0–
– 15
3–
30 –
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
13.
Test conditions assume signal transition time of 1.8 ns or less,
IOL/IOH and load capacitance shown in Figure 3 on page 10.
timing
reference
levels
of
VCCQ/2,
input
pulse
levels
of
0
to
VCC
Q(typ),
and
output
loading
of
the
specified
14. WE must be HIGH during SRAM read cycles.
15. Device is continuously selected with CE, OE and BHE / BLE LOW.
16. These parameters are guaranteed by design but not tested.
17. Measured ±200 mV from steady state output voltage.
18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19. HSB must remain HIGH during read and write cycles.
Document #: 001-53954 Rev. *F
Page 11 of 22
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| PDF Descargar | [ Datasheet CY14V104NA.PDF ] | |
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