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CY14C512Q Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14C512Q
Beschreibung 512-Kbit (64 K x 8) SPI nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
CY14C512Q Datasheet, Funktion
CY14C512Q
CY14B512Q
CY14E512Q
512-Kbit (64 K × 8) SPI nvSRAM
512-Kbit (64 K × 8) SPI nvSRAM
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Support automatic STORE on power-down with a small
capacitor (except for CY14X512Q1A)
High reliability
Infinite read, write, and RECALL cycles
1million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
40-MHz, and 104-MHz High-speed serial peripheral interface
(SPI)
40-MHz clock rate SPI write and read with zero cycle delay
104-MHz clock rate SPI write and SPI read (with special fast
read instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 150 A
Sleep mode current of 8 A
Logic Block Diagram
VCC VCAP
Industry standard configurations
Operating voltages:
• CY14C512Q: VCC = 2.4 V to 2.6 V
• CY14B512Q: VCC = 2.7 V to 3.6 V
• CY14E512Q: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14X512Q combines a 512-Kbit nvSRAM[1] with
a nonvolatile element in each memory cell with serial SPI
interface. The memory is organized as 64 K words of 8 bits each.
The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14X512Q1A). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). You can also initiate the STORE
and RECALL operations through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14X512Q1A
No
Yes
CY14X512Q2A
Yes
Yes
CY14X512Q3A
Yes
Yes
No No Yes
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacture ID/
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantrumTrap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
WRSR/RDSR/WREN
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-65267 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 5, 2011
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CY14C512Q Datasheet, Funktion
CY14C512Q
CY14B512Q
CY14E512Q
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the ready status of the device.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. A
Software RECALL is issued by using the SPI instruction for
RECALL.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14X512Q2A/CY14X512Q3A has AutoStore enabled
from the factory. In CY14X512Q1A, VCAP pin is not present and
AutoStore option is not available. The AutoStore Enable and
Disable instructions to CY14X512Q1A are ignored.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled in any case.
Serial Peripheral Interface
SPI Overview
The SPI is a four- pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X512Q provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X512Q can run at speeds up to
104 MHz except READ instruction.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X512Q operates as a SPI slave and may share the SPI bus
with other SPI slave devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14X512Q enables SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission - SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X512Q has two separate pins for SI and SO, which can be
connected with the master as shown in Figure 4 on page 7.
Document #: 001-65267 Rev. *B
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CY14C512Q pdf, datenblatt
CY14C512Q
CY14B512Q
CY14E512Q
Therefore, WREN instruction needs to be used before a new
write instruction is issued.
Figure 10. WREN Instruction
CS
SCK
01 234567
SI 0 0 0 0 0 1 1 0
SO HI-Z
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 11. WRDI Instruction
CS
SCK
01 234567
SI 0 0 0 0 0 1 0 0
SO HI-Z
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
Block Protect bits.
Table 5. Block Write Protect Bits
Level
0
1 (1/4)
2 (1/2)
3 (All)
Status Register
Bits
BP1 BP0
00
01
10
11
Array Addresses Protected
None
0xC000-0xFFFF
0x8000-0xFFFF
0x0000-0xFFFF
Hardware Write Protection (WP)
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
Note CY14X512Q2A does not have WP pin and therefore does
not provide hardware write protection.
Table 6 summarizes all the protection features of this device
Table 6. Write Protection Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
X X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 LOW 1 Protected Writable Protected
1 HIGH 1 Protected Writable
Writable
Document #: 001-65267 Rev. *B
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