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CY14B512J Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14B512J
Beschreibung 512-Kbit (64 K x 8) Serial (I2C) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
CY14B512J Datasheet, Funktion
CY14C512J
CY14B512J, CY14E512J
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14X512J1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
High speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast-mode Plus: 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one-quarter, one-half, or entire
array
I2C access to special functions
Nonvolatile STORE/RECALL
8 byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 150 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C512J: VCC = 2.4 V to 2.6 V
• CY14B512J: VCC = 2.7 V to 3.6 V
• CY14E512J: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C512J/CY14B512J/CY14E512J combines a
512-Kbit nvSRAM[1] with a nonvolatile element in each memory
cell. The memory is organized as 64 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X512J1). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through I2C commands.
Configuration
Feature
CY14X512J1 CY14X512J2 CY14X512J3
AutoStore
No Yes Yes
Software STORE
Yes
Yes
Yes
Hardware STORE
No
No Yes
Slave Address pins A2, A1, A0
A2, A1
A2, A1, A0
Logic Block Diagram
VCC VCAP
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
Note
1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Quantrum Trap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-65232 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 4, 2011
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CY14B512J Datasheet, Funktion
CY14C512J
CY14B512J, CY14E512J
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Figure 6. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
not acknowledge (A)
acknowledge (A)
SCL FROM
MASTER
S
START
condition
1
2
89
clock pulse for
acknowledgement
High Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device into high speed mode. This enables master slave
communication for speed upto 3.4 MHz. A stop condition exits
Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
F/S-mode
Hs-mode
F/S-mode
S MASTER CODE A Sr SLAVE ADD. R/W A
DATA
A/A P
n (bytes+ack.)
Hs-mode continues
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
Sr SLAVE ADD.
continue data transfer in Hs-mode, the master sends Repeated
START (Sr). See Figure 13 on page 11 and
Figure 16 on page 12 for Hs-mode timings for read and write
operation.
Document #: 001-65232 Rev. *B
Page 6 of 31
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CY14B512J pdf, datenblatt
CY14C512J
CY14B512J, CY14E512J
Current nvSRAM Read
Each read operation starts with the master transmitting the
nvSRAM slave address with the LSB set to ‘1’ to indicate “Read”.
The reads start from the address on the address counter. The
address counter is set to the address location next to the last
accessed with a “Write” or “Read” operation. The master may
terminate a read operation after reading 1 byte or continue
reading addresses sequentially till the last address in the
memory after which the address counter rolls back to the
address 0x0000. The valid methods of terminating read access
are described in Section Read Operation on page 10.
Figure 15. Current Location Single-Byte nvSRAM Read (except Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 A0 1
A
Data Byte
S
AT
0
P
P
Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 A0 1
A
S
AT
0
P
P
Data Byte
A
Data Byte N
Figure 17. Current Location Single-Byte nvSRAM Read (Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Hs-mode command
T
S00 0 01 XX X
Memory Slave Address
Sr 1 0 1 0 A2 A1 A0 1
AA
Data Byte
S
AT
0
P
P
Figure 18. Current Location Multi-Byte nvSRAM Read (Hs-mode)
By Master
SDA Line
S
T
A
R Hs-mode command
T
S00 0 01 XX X
Memory Slave Address
Sr 1 0 1 0 A2 A1 A0 1
By nvSRAM
AA
Data Byte
A
Data Byte N
S
A
T
0
P
P
Document #: 001-65232 Rev. *B
Page 12 of 31
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