Datenblatt-pdf.com


CY14C064PA Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14C064PA
Beschreibung 64-Kbit (8 K x 8) SPI nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
CY14C064PA Datasheet, Funktion
CY14C064PA
CY14B064PA
CY14E064PA
64-Kbit (8 K × 8) SPI nvSRAM
with Real Time Clock
64-Kbit (8 K × 8) SPI nvSRAM with Real Time Clock
Features
64-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 8 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power Up RECALL)
or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real time clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 µA (typical)
40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and read (with special fast read
instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 250 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C064PA : VCC = 2.4 V to 2.6 V
• CY14B064PA : VCC = 2.7 V to 3.6 V
• CY14E064PA : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14X064PA combines a 64 Kbit nvSRAM[1] with
a full-featured RTC in a monolithic integrated circuit with serial
SPI interface. The memory is organized as 8 K words of 8 bits
each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
You can also initiate the STORE and RECALL operations
through SPI instruction.
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacture ID/
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantrumTrap
8Kx8
SRAM
8Kx8
STORE
RECALL
RDRTC/WRTC
WRSR/RDSR/WREN
Status Register
Xin
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-68249 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 6, 2011
[+] Feedback






CY14C064PA Datasheet, Funktion
CY14C064PA
CY14B064PA
CY14E064PA
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X064PA provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X064PA can run at speeds up to
104 MHz except RDRTC and READ instruction.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. CY14X064PA supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X064PA operates as a slave device and may share the SPI
bus with multiple CY14X064PA devices or other SPI devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW.
The CY14X064PA is selected when the CS pin is LOW. When
the device is not selected, data through the SI pin is ignored and
the serial output pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14X064PA allows SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X064PA has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 64-Kbit serial nvSRAM requires a 2-byte address for any
read or write operation. However, since the address is only
13 bits, it implies that the first three bits which are fed in are
ignored by the device. Although these three bits are ‘don’t care’,
Cypress recommends that these bits are treated as 0s to enable
seamless transition to higher memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X064PA uses the standard opcodes for memory accesses.
In addition to the memory accesses, CY14X064PA provides
additional opcodes for the nvSRAM specific functions: STORE,
RECALL, AutoStore Enable, and AutoStore Disable. Refer to
Table 1 on page 9 for details on opcodes.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS and the SO pin remains tri-stated.
Status Register
CY14X064PA has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 3 on page 10.
Document #: 001-68249 Rev. *A
Page 6 of 43
[+] Feedback

6 Page









CY14C064PA pdf, datenblatt
CY14C064PA
CY14B064PA
CY14E064PA
.
Figure 9. WREN Instruction
CS
SCK
01 234567
SI 0 0 0 0 0 1 1 0
HI-Z
SO
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ to protect the device against inadvertent writes. This
instruction is issued following the falling edge of CS followed by
opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
CS
SCK
01 234567
SI 0 0 0 0 0 1 0 0
HI-Z
SO
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 4 shows the function of
Block Protect bits.
Table 4. Block Write Protect Bits
Level
0
1 (1/4)
2 (1/2)
3 (All)
Status Register Bits
Array Addresses Protected
BP1 BP0
00
None
01
0x1800-0x1FFF
10
0x1000-0x1FFF
11
0x0000-0x1FFF
Hardware Write Protection (WP Pin)
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
Table 5 summarizes all the protection features provided in the
CY14X064PA.
Table 5. Write Protection Operation
WPEN WP
XX
0X
1 LOW
1 HIGH
WEN
Protected Unprotected
Blocks
Blocks
Status
Register
0 Protected Protected Protected
1 Protected Writable Writable
1 Protected Writable Protected
1 Protected Writable Writable
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) Instruction
The read operations on this device are performed by giving the
instruction on the SI pin and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by two bytes
of address (A12-A0). The most significant address bits
(A15-A13) are don’t cares. After the last address bit is
transmitted on the SI pin, the data (D7-D0) at the specific
address is shifted out on the SO line on the falling edge of SCK
starting with D7. Any other data on SI line after the last address
bit is ignored.
CY14X064PA allows reads to be performed in bursts through
SPI which can be used to read consecutive addresses without
issuing a new READ instruction. If only one byte is to be read,
the CS line must be driven HIGH after one byte of data comes
out. However, the read sequence may be continued by holding
the CS line LOW and the address is automatically incremented
and data continues to shift out on SO pin. When the last data
memory address (0x1FFF) is reached, the address rolls over to
0x0000 and the device continues to read.
Fast Read Sequence (FAST_READ) Instruction
The FAST_READ instruction allows you to read memory at SPI
frequency above 40 MHz and up to 104 MHz (Max). The host
system must first select the device by driving CS LOW, the
FAST_READ instruction is then written to SI, followed by 2
address byte (A12-A0) and then a dummy byte. The most
significant address bits (A15-A13) are don’t cares.
From the subsequent falling edge of the SCK, the data of the
specific address is shifted out serially on the SO line starting with
MSB. The first byte specified can be at any location. The device
Document #: 001-68249 Rev. *A
Page 12 of 43
[+] Feedback

12 Page





SeitenGesamt 30 Seiten
PDF Download[ CY14C064PA Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CY14C064PA64-Kbit (8 K x 8) SPI nvSRAMCypress Semiconductor
Cypress Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche