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PDF MB81EDS516545 Data sheet ( Hoja de datos )
| Número de pieza | MB81EDS516545 | |
| Descripción | 512M Bit (4 bank x 2M word x 64 bit) | |
| Fabricantes | Fujitsu | |
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FUJITSU MICROELECTRONICS
DATA SHEET
DS05-11463-1E
MEMORY Consumer FCRAMTM
CMOS
512M Bit (4 bank x 2M word x 64 bit)
Consumer Applications Specific Memory for SiP
MB81EDS516545
■ DESCRIPTION
The Fujitsu MB81EDS516545 is a CMOS Fast Cycle Random Access Memory (FCRAM*) with Low Power Double
Data Rate (LPDDR) SDRAM Interface containing 536, 870, 912 storages accessible in a 64-bit format.
MB81EDS516545 is suited for consumer application requiring high data band width with low power consumption.
* : FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan
■ FEATURES
• 2 M word × 64 bit × 4 banks organization
• DDR Burst Read/Write Access Capability
-tCK = 4.6 ns Min / 216 MHz Max (Tj ≤ + 105 °C)
-tCK = 5 ns Min / 200 MHz Max (Tj ≤ + 125 °C)
• Low Voltage Power Supply: VDD = VDDQ + 1.7 V to + 1.9 V
• Junction Temperature:
TJ = − 10 °C to + 125 °C
• 1.8 V-CMOS compatible inputs
• Unidirectional READ Data Strobe per 2 byte
• Unidirectional WRITE Data Strobe per 2 byte
• Burst Length: 2, 4, 8, 16
• CAS latency: 2, 3, 4
• Clock Stop capability during idle periods
• Auto Precharge option for each burst access
• Configurable Driver Strength and Pre Driver Strength
• Auto Refresh and Self Refresh Modes
• Deep Power Down Mode
• Low Power Consumption
-IDD4R =330 mA Max @ 3.46 GByte/s
-IDD4W =380 mA Max @ 3.46 GByte/s
• 8 K refresh cycles /16.7 ms (Tj ≤ +125 °C)
(Continued)
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
www.DataSheet4U.net
1 page  
MB81EDS516545
6. Address Inputs (A0 to A12)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix. Total 21
address input signals are required to decode such a matrix. Row Address (RA) is input from A0 to A12 and
Column Address (CA) is input from A0 to A7. Row addresses are latched with ACTIVE (ACT or MACT) com-
mands, and Column addresses and Auto Precharge (AP) bit are latched with Read (READ or READA) or Write
command (WRIT or WRITA).
• Command and address inputs setup and hold time
CK
Command
(CS, RAS, CAS, WE)
Address
tIS tIH
tIPW
7. Input Data Mask (DM0 to DM7)
DM is an input mask signal for write data. Input data is masked when DM is sampled High on the both edges
of WDQS along with input data. DM0, DM1, DM2, DM3, DM4, DM5, DM6 and DM7 correspond to DQ[7:0],
DQ[15:8], DQ[23:16], DQ[31:24], DQ[39:32], DQ[47:40], DQ[55:48] and DQ[63:56] respectively. Refer to the
“DQ/RDQS/WDQS/DM Correspondence Table”.
8. Data Bus Input / Output (DQ0 to DQ63)
DQ is data bus input / output signal.
9. Read Data Strobe (RDQS0 to RDQS3)
RDQS is output signal transmitted by memory during read operation. RDQS is edge aligned with output data.
RDQS0, RDQS1, RDQS2 and RDQS3 correspond to DQ[15:0], DQ[31:16], DQ[47:32] and DQ[63:48] respec-
tively. Refer to the “DQ/RDQS/WDQS/DM Correspondence Table”.
After stable power supply, RDQS outputs Low.
DS05-11463-1E
5
5 Page 
MB81EDS516545
3. Burst Length (BL)
Burst Length (BL) is the number of word to be read or write as the result of a single READ or WRITE command.
It can be set on 2, 4, 8, 16 words boundary through Mode Register. The burst type is sequential that is incremental
decoding scheme within a boundary address to be determined by burst length. Device internal address counter
assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least
significant address ( = 0).
Burst
Length
Starting Column Address
A3 A2 A1 A0
Burst Address Sequence
(Hexadecimal)
XXX0
2
XXX1
0-1
1-0
XX0 0
0-1-2-3
XX0 1
4
XX1 0
1-2-3-0
2-3-0-1
XX1 1
3-0-1-2
X000
0-1-2-3-4-5-6-7
X001
1-2-3-4-5-6-7-0
X010
2-3-4-5-6-7-0-1
X011
8
X100
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
X101
5-6-7-0-1-2-3-4
X110
6-7-0-1-2-3-4-5
X111
7-0-1-2-3-4-5-6
0000
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0001
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
0010
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
0011
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
0100
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
0101
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
0110
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
0111
16
1000
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1001
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
1010
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
1011
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
1100
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
1101
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
1110
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
1111
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
DS05-11463-1E
11
11 Page | ||
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| PDF Descargar | [ Datasheet MB81EDS516545.PDF ] | |
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