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YSS944 Schematic ( PDF Datasheet ) - YAMAHA

Teilenummer YSS944
Beschreibung (YSS940 - YSS944) ADAMB Advanced Digital Audio Multi channel decode processor
Hersteller YAMAHA
Logo YAMAHA Logo 




Gesamt 30 Seiten
YSS944 Datasheet, Funktion
YSS944/943/940
ADAMB
Advanced Digital Audio Multi channel decode processor
„ Outline
The YSS944 (ADAMB-f)/YSS943 (ADAMB-b)/YSS940 (ADAMB-nd) is an audio decoding digital signal
processor that integrates onto a single chip the various digital signal processing functions required for AV
amplifiers, etc. It includes an advanced 32-bit floating-point DSP and is able to decode a variety of audio
formats.
[Note]
The contents described in this manual are implemented by downloading boot firmware.
For detailed information about the boot firmware, please contact YAMAHA.
The YSS943 cannot execute DTS-ES and DTS Neo:6 decoding.
The YSS940 cannot execute any decoding related to DTS (DTS, DTS-ES, DTS 96/24, and DTS Neo:6).
„ Features
Supports various types of decoding up to 7.1 channels (5.1/6.1/7.1 channels selectable).
5.1-channel decoding of Dolby Digital (AC-3), DTS, AAC.
6.1-channel decoding of Dolby Digital EX, DTS-ES.
DTS 96/24 decoding and audio interface clock division/switching functions.
Dolby Pro Logic IIx and DTS Neo:6 decoding
Tone control and bass management functions
Function modification/expansion by downloading firmware to on-chip memory
Lip-sync function that enables synchronization of voice and video with variable voice delay
Supports sampling frequencies up to 192 kHz during PCM playback.
1/2 down sampling function when two PCM channels are played back
Dolby Digital/DTS/AAC decode information output function (can be read by microprocessor)
High-speed/high-accuracy operation by 32-bit floating-point DSP
Operating frequency: 180 MHz (178.176 MHz)
Data bus width: 32 bits (24-bit mantissa and 8-bit exponent)
Multiplier/adder: 32 bits × 32 bits + 55 bits 55 bits (47-bit mantissa and 8-bit exponent)
No external memory needed (external memory is used when delay is increased.)
Eight general I/O ports
On-chip PLL for generation of high-speed internal operating clock
Supply voltage: 1.2 V (core block) and 3.3 V (pin block)
Low power consumption: about 210 mW (standard value during Dolby Digital decoding)
Si-gate CMOS process
Lead-free plating LQFP144 package (YSS944-VZ, YSS943-VZ, and YSS940-VZ)
[Note]
“Dolby,” ”Dolby Pro Logic IIx,” and “AC-3” are trademarks of Dolby Laboratories.
“DTS,” “DTS-ES,” “DTS 96/24,” and “DTS Neo:6” are trademarks of Digital Theater Systems, Inc.
„ Applications
AV amplifiers for home theaters
Car audio systems
www.DataSheet4U.com
YSS944/943/940 CATALOG
CATALOG No.: LSI-4SS944A31
2005.6






YSS944 Datasheet, Funktion
Type
Initial clear
Clock
Microprocessor
interface
Audio interface
YSS944/943/940
Pin Pin Name I/O
Function
No. Note 1)
61
62
69
77
78
86
87
93
94
105
106
117
118
123
129
130
139
140
1 AHVSS
Ground pin 2 for PLL analog block.
Be sure to insert a 0.1 µF capacitor between the AHVDD and AHVSS
pins.
2 AHVSSG
Ground pin 3 for PLL analog block.
Be sure to insert a 0.1 µF capacitor between the AHVDDG and
AHVSSG pins.
3 DVSS
Ground pin for PLL digital block.
Be sure to insert a 0.1 µF capacitor between the DVDD and DVSS
pins.
141 AVSSR
Ground pin 1 for PLL analog block.
Be sure to insert a 0.1 µF capacitor between the AVDDR and AVSSR
pins.
131 nIC
Is Hardware reset input pin
The LSI is initialized when this pin is at low level.
18 XI
I Clock input pin.
Connect this pin as shown in the circuit example Note 2) of the
12.288 MHz crystal oscillator.
If not connected to a crystal oscillator, input a 12.288 MHz clock to
this pin.
19 XO
O This is the output pin for the crystal oscillator.
Connect this pin as shown in the circuit example Note 2).
If not connected to a crystal oscillator and inputting directly to the XI
pin, do not connect anything to this pin. Do not use this pin for any
purpose other than clock oscillation.
126 nMICS
Is This is the microprocessor interface’s chip select input pin.
Input to the MISCK and MISI pins becomes valid when this pin is at
low level.
125 MISCK
Is This is the microprocessor interface’s clock input pin.
124 MISI
I This is the microprocessor interface’s address read/write control and
data input pin.
122 MISO
Ot This is the microprocessor interface’s data output pin.
Connect a pull-up resistor.
32 SDIMCK
Is This is the master clock input pin for the audio interface’s input side.
The master clock is input from DIR, ADC, etc.
The highest clock frequency that can be input is 25 MHz.
(The clock rate is 512 fs when the input sampling frequency is 48 kHz
or less, 256 fs when the frequency is 96 kHz, and 128 fs when the
frequency is up to 192 kHz.)
31 SDIBCK
Is This is the bit clock I/O pin for the audio interface’s input side.
6

6 Page









YSS944 pdf, datenblatt
YSS944/943/940
„ Microprocessor Interface
External microprocessor or similar devices use this microprocessor interface (4-wire serial interface) to
perform the following tasks.
Access to registers
Firmware download to on-chip memory
(1) Register access
Registers are accessed in 16-bit units via the microprocessor interface. MISI is used to specify the register’s
address (7 bits: A6 to A0) and the read/write option (1 bit:R/W). During a write operation (R/W=L), data (8
bits: D7 to D0) is input to MISI and during a read operation (R/W=H) 8-bit data is output from the MISO pin.
The data to be written is stored in the register at the rising edge of MISCK during the last data bit (D7 in
figure).
The microprocessor interface’s sequence when accessing registers is shown below.
nMICS
MISCK
MISI
Don't care A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D3 D4 D5 D6 D7
Don't care
MISO
High-Z
During
write
operation
(R/W = L)
MISI
Don't care A0 A1 A2 A3 A4 A5 A6 R/W
Don't care
Don't care
MISO
High-Z
D0 D1 D2 D3 D4 D5 D6 D7
High-Z
During
read
operation
(R/W = H)
[Note]
MISO is in output mode only when nMICS is at low level and during the data (8 bits) output timing.
Otherwise, it is in high impedance (High-Z) mode and MISCK, MISI, and MISO can be shared for devices
that have a similar interface.
Registers can be accessed continuously while nMICS remains at low level. There is no need to
repeatedly set nMICS to high level.
Certain register settings enable nMICS to be shared by multiple LSIs.
Access to on-chip memory (firmware download) is performed by combining with control of writing to a
register
Operation during a hardware reset (when nIC is at low level):
During a hardware reset, the microprocessor interface does not function. Also, MISO is fixed at high
impedance (High-Z). When nIC is at low level, nMICS should be initialized to high level.
Interruption of access:
Access can be interrupted by setting nMICS to high level. The write operation prior to the 16th rising
edge of MISCK (MISI’s D7 data capture clock) described above becomes invalid. The MISO pin is set
to high impedance (High-Z).
12

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