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Teilenummer | 64F2506 |
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Beschreibung | HD64F2506 | |
Hersteller | Renesas Technology | |
Logo | ||
Gesamt 70 Seiten To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
www.DataSheet4U.com
Configuration of This Manual
This manual comprises the following items:
1. General Precautions in the Handling of MPU/MCU Products
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions for This Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
Thiswdwoews.DnoattainSchleuedte4Ual.lcoomf the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 6.00 Sep. 24, 2009 Page iv of xlvi
REJ09B0099-0600
6 Page 2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC) ...................................... 55
2.7.8 Memory Indirect⎯@@aa:8 ................................................................................... 55
2.7.9 Effective Address Calculation ................................................................................ 56
2.8 Processing States.................................................................................................................. 59
2.9 Usage Notes ......................................................................................................................... 61
2.9.1 TAS Instruction ...................................................................................................... 61
2.9.2 STM/LDM Instruction............................................................................................ 61
2.9.3 Bit Manipulation Instructions ................................................................................. 61
2.9.4 Access Method for Registers with Write-Only Bits ............................................... 63
Section 3 MCU Operating Modes ......................................................................... 67
3.1 Operating Mode Selection ................................................................................................... 67
3.2 Register Descriptions........................................................................................................... 68
3.2.1 Mode Control Register (MDCR) ............................................................................ 68
3.2.2 System Control Register (SYSCR)......................................................................... 68
3.3 Operating Mode ................................................................................................................... 70
3.3.1 Mode 6.................................................................................................................... 70
3.3.2 Mode 7.................................................................................................................... 70
3.3.3 Pin Functions .......................................................................................................... 70
3.4 Address Map in Each Operating Mode................................................................................ 72
Section 4 Exception Handling ............................................................................... 75
4.1 Exception Handling Types and Priority............................................................................... 75
4.2 Exception Sources and Exception Vector Table .................................................................. 75
4.3 Reset .................................................................................................................................... 77
4.3.1 Types of Reset ........................................................................................................ 77
4.3.2 Reset Exception Handling ...................................................................................... 78
4.3.3 Interrupts after Reset............................................................................................... 79
4.3.4 State of On-Chip Peripheral Modules after Reset Release ..................................... 79
4.4 Trace Exception Handling ................................................................................................... 79
4.5 Interrupt Exception Handling .............................................................................................. 80
4.6 Trap Instruction Exception Handling................................................................................... 80
4.7 wwSwta.cDkaStatSatheeaeft4teUr.Ecoxmception Handling .................................................................................. 82
4.8 Usage Note........................................................................................................................... 82
Section 5 Interrupt Controller................................................................................ 85
5.1 Features................................................................................................................................ 85
5.2 Input/Output Pins................................................................................................................. 87
5.3 Register Descriptions........................................................................................................... 88
5.3.1 Interrupt Priority Registers A to M, and O (IPRA to IPRM, IPRO)....................... 89
Rev. 6.00 Sep. 24, 2009 Page x of xlvi
REJ09B0099-0600
12 Page | ||
Seiten | Gesamt 70 Seiten | |
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