K8A57EBC Datasheet PDF - Samsung semiconductor
| Part Number | K8A57EBC | |
| Description | 256Mb C-die NOR FLASH | |
| Manufacturers | Samsung semiconductor | |
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Rev. 1.0, Nov. 2010
K8A56(57)ET(B)(Z)C
256Mb C-die NOR FLASH
16M x16, Synch Burst
Multi Bank SLC NOR Flash
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
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K8A56(57)15ET(B)(Z)C
datasheet
NOR
FLASH
Rev.
MEMORY
1.0
256M Bit (16M x16) Synch Burst , Multi Bank SLC NOR Flash Memory
1.0 FEATURES
2.0 GENERAL DESCRIPTION
• Single Voltage, 1.7V to 1.95V for Read and Write operations
The K8A(56/57)15E featuring single 1.8V power supply is a 256Mbit Burst
• Organization
Multi Bank Flash Memory organized as 16Mx16. The memory architecture
- 16,777,216 x 16 bit ( Word Mode Only)
of the device is designed to divide its memory arrays into 256 blocks(Uni-
• Read While Program/Erase Operation
form block part)/259 blocks(Boot block part) with independent hardware
• Multiple Bank Architecture
protection. This block architecture provides highly flexible erase and pro-
- 16 Banks (16Mb Partition)
gram capability. The K8A(56/57)15E NOR Flash consists of sixteen banks.
• OTP Block : Extra 512-Word block
This device is capable of reading data from one bank while programming or
• Read Access Time (@ CL=30pF)
erasing in the other bank.
- Asynchronous Random Access Time : 100ns
Regarding read access time, the K8A5615E provides an 11ns burst access
- Synchronous Random Access Time :95ns
time and an 95ns initial access time at 66MHz. At 83MHz, the K8A5615E
- Burst Access Time :
provides an 9ns burst access time and an 95ns initial access time. At
11ns(66Mhz) / 9ns(83Mhz) / 7ns (108MHz) / 6ns (133MHz)
108MHz, the K8A5715E provides an 7ns burst access time and an 95ns ini-
• Page Mode Operation
tial access time. At 133MHz, the K8A5715E provides an 6ns burst access
16Words Page access allows fast asynchronous read
time and an 95ns initial access time.
Page Read Access Time :
The device performs a program operation in units of 16 bits (Word) and
18ns(66/83Mhz) / 15ns(108/133Mhz)
erases in units of a block. Single or multiple blocks can be erased. The
• Burst Length :
block erase operation is completed within typically 0.6sec. The device
- Continuous Linear Burst
requires 25mA as program/erase current in the extended temperature
- Linear Burst : 8-word & 16-word with Wrap
ranges.
• Block Architecture
The K8A(56/57)15E NOR Flash Memory is created by using Samsung's
- Uniform block part (K8A(56/57)15EZC) : Two hundred fifty-six
advanced CMOS process technology.
64Kword blocks
- Boot block part (K8A(56/57)15ET(B)C) : Four 16Kword blocks and two
3.0 PIN DESCRIPTIONhundred fifty-five 64Kword blocks (Bank 0 contains four 16 Kword blocks
and fifteen 64Kword blocks, Bank 1 ~ Bank 15 contain two hundred forty
64Kword blocks)
Pin Name
Pin Function
• Reduce program time using the VPP
A0 - A23
Address Inputs
• Support 32-word Buffer Program
• Power Consumption (Typical value, CL=30pF)
- Synchronous Read Current : 35mA
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
• Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=VIL
(Boot block part : K8A(56/57)15ET(B)C)
- Last one block (BA255) is protected by WP=VIL
(Uniform block part : K8A(56/57)15EZC)
- All blocks are protected by VPP=VIL
• Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
• Erase Suspend/Resume
• Program Suspend/Resume
• Unlock Bypass Program/Erase
• Hardware Reset (RESET)
• Deep Power Down Mode
• Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
• Endurance
- 100K Program/Erase Cycles Minimum
• Extended Temperature : -25°C ~ 85°C
• Support Common Flash Memory Interface
• Output Driver Control by Configuration Register
• Low Vcc Write Inhibit
w• wPawck.Dagaeta:SThBeDet4U.com
DQ0 - DQ15
CE
OE
RESET
VPP
WE
WP
CLK
RDY
AVD
DPD
Vcc
VSS
Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Deep Power Down
Power Supply
Ground
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ K8A57EBC.PDF Datasheet ] | |
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