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K524G2GACB-A050 Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K524G2GACB-A050
Beschreibung 4Gb NAND Flash + 2Gb Mobile DDR
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 30 Seiten
K524G2GACB-A050 Datasheet, Funktion
K524G2GACB-A050
MCP MEMORY
MCP Specification
4Gb NAND Flash + 2Gb Mobile DDR
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
www.DataSheeatp4pUli.ccaotmions where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Revision 1.3
November 2009






K524G2GACB-A050 Datasheet, Funktion
K524G2GACB-A050
5. PIN DESCRIPTION
Pin Name
CKd,/CKd
CKEd
/CSd
/RASd
/CASd
/WEd
A0d ~ A13d
BA0d ~ BA1d
DM0d ~ DM3d
DQS0d~DQS3d
DQ0d ~ DQ31d
VDDd
VDDQd
VSSd
VSSQd
Pin Function(M-DDR)
System Clock & Differential Clock
Clock Enable
Chip Selection
Row Address Strobe
Column Address Strobe
Write Enable
Address Input
Bank Address Input
Input Data Mask
Data Input / Output
Data Input / Output
Power Supply
Data Out Power
Ground
DQ Ground
MCP MEMORY
Pin Name
/CEn
/REn
/WPn
/WEn
ALEn
CLEn
R/Bn
IO0n ~ IO15n
VCCn
VSSn
Pin Function(NAND Flash)
Chip Enable
Read Enable
Write Protection
Write Enable
Address Latch Enable
Command Latch Enable
Ready/Busy Output
Data Input/Output
Power Supply
Ground
Pin Name
NC
DNU
Pin Function
No Connection
Do Not Use
www.DataSheet4U.com
- 6 - Revision 1.3
November 2009

6 Page









K524G2GACB-A050 pdf, datenblatt
K524G2GACB-A050
MCP MEMORY
Figure 3. Functional Block Diagram(x16)
VCC
VSS
A11 - A29*
X-Buffers
Latches
& Decoders
4,096M + 128M Bit for 4Gb
8,192M + 256M Bit for 8Gb DDP
NAND Flash
ARRAY
A0 - A10
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
CE Control Logic
RE & High Voltage
WE Generator
CLE ALE WP
I/O Buffers & Latches
Global Buffers
Output
Driver
VCC
VSS
I/0 0
I/0 15
Figure 4. Figure 2-2. Array Organization(x16)
1 Block = 64 Pages
(64K + 2K)Word
4,096 blocks for 4Gb
8,192 blocks for 8Gb DDP
1K Words
32 Words
1 Page = (1K + 32)Word
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K)Words
1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks
= 4,224 Mbits for 4Gb
16 bit 1 Device = (1K + 32)Word x 64Pages x 8,192 Blocks
= 8,448 Mbits for 8Gb DDP
I/O 0 I/O 1
Page Register
1K Words
I/O 0 ~ I/O 15
32 Words
Table 2. Array address : (x16)
I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8~I/O 15
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9 A10 *L
*L
*L
*L
*L
3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18
4th Cycle A19 A20 A21 A22 A23 A24 A25 A26
www.Dat5atShhCeyectl4eU.comA27
A28 *A29
*L
*L
*L
*L
*L
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* A29 is Row address for 8G DDP.
In case of 4G Mono, A29 must be set to "Low"
*L
*L
*L
*L
*L
Address
Column Address
Column Address
Row Address
Row Address
Row Address
- 12 -
Revision 1.3
November 2009

12 Page





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