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K522H1HACF-B050 Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K522H1HACF-B050
Beschreibung 2Gb (128M x16) NAND Flash + 1Gb (64M x16 ) Mobile DDR SDRAM
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 30 Seiten
K522H1HACF-B050 Datasheet, Funktion
Rev. 1.0, Oct. 2010
K522H1HACF-B050
MCP Specification
2Gb (128M x16) NAND Flash + 1Gb (64M x16 ) Mobile DDR SDRAM
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
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www.DataSAhlel berta4nUd.cnoammes, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
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K522H1HACF-B050 Datasheet, Funktion
K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
4. PIN DESCRIPTION
Pin Name
IO0n ~ IO15n
R/Bn
/REn
/WEn
ALEn
/WPn
/CEn
CLEn
VCCn
VSSn
Pin Function(NAND Flash)
Data Input/Output
Ready/Busy Output
Read Enable
Write Enable
Address Latch Enable
Write Protection
Chip Enable
Command Latch Enable
Power Supply
Ground
Pin Name
DNU
NC
Pin Function
Do Not Use
No Connected
Pin Name
CKd, /CKd
CKEd
/CSd
/RASd
/CASd
/WEd
A0d ~ A13d
BA0d ~ BA1d
LDMd,UDMd
LDQSd , UDQSd
DQ0d ~ DQ15d
VDDd
VDDQd
VSSd
VSSQd
Pin Function(Mobile DDR)
System Clock & Differential Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Input
Bank Select Address
Lower / Upper Input Data Mask
Lower / Upper Data Strobe
Data Input/Output
Power Supply
Data Out Power
Ground
DQ Ground
www.DataSheet4U.com
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6 Page









K522H1HACF-B050 pdf, datenblatt
K522H1HACF-B050
datasheet
Rev. 1.0
MCP Memory
Figure 3. unctional Block Diagram(x16)
VCC
VSS
A11 - A28*
X-Buffers
Latches
& Decoders
2,048M + 64M Bit for 2Gb
4,096M + 128M Bit for 4Gb DDP
NAND Flash
ARRAY
A0 - A10
Y-Buffers
Latches
& Decoders
Data Register & S/A
Y-Gating
Command
Command
Register
CE Control Logic
RE & High Voltage
WE Generator
CLE ALE WP
I/O Buffers & Latches
Global Buffers
Output
Driver
VCC
VSS
I/0 0
I/0 15
Figure 4. Figure 2-2. Array Organization(x16)
1 Block = 64 Pages
(64K + 2K)Word
2,048 blocks for 2Gb
4,096 blocks for 4Gb DDP
1K Words
32 Words
1 Page = (1K + 32)Word
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K)Words
1 Device = (1K + 32)Word x 64Pages x 2,048 Blocks
= 2,112 Mbits for 2Gb
16 bit 1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks
= 4,224 Mbits for 4Gb DDP
Page Register
1K Words
I/O 0 ~ I/O 15
32 Words
[Table 2] Array address : (x16)
I/O
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
1st Cycle A0 A1 A2 A3 A4 A5 A6
2nd Cycle
A8
A9 A10 *L
*L
*L
*L
3rd Cycle A11 A12 A13 A14 A15 A16 A17
4th Cycle A19 A20 A21 A22 A23 A24 A25
5th Cycle
A27 *A28
*L
*L
*L
*L
*L
NOTE :
Column Address : Starting Address of the Register.
w** LTwhmewuds.etDvbiecaetsaeigStnthooer"eeLsto4awnU"y. .acdodmitional input of address cycles than required.
* A28 is Row address for 4G DDP.
In case of 2G Mono, A28 must be set to "Low"
I/O 7
A7
*L
A18
A26
*L
I/O 8~I/O 15
*L
*L
*L
*L
*L
Address
Column Address
Column Address
Row Address
Row Address
Row Address
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