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CY14C101J Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14C101J
Beschreibung 1-Mbit (128 K X 8) Serial (I2C) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
CY14C101J Datasheet, Funktion
CY14C101J
PRELIMINARY
CY14B101J, CY14E101J
1 Mbit (128 K × 8) Serial (I2C) nvSRAM
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
Internally organized as 128 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL
CALL) or
to
by
IS2CRAcMomimniatiantded(SoofntwpaoreweRrE-uCpA(LPLo)wer-Up
RE-
Automatic STORE on power-down with a small capacitor (ex-
cept for CY14X101J1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
High speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast-mode Plus: 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for 1/4, 1/2, or entire array
I2C access to special functions
Nonvolatile STORE/RECALL
8 byte serial number
Manufacturer ID and Product ID
Sleep mode
Industry standard configurations
Operating voltages:
• CY14C101J: VCC = 2.4 V to 2.6 V
• CY14B101J: VCC = 2.7 V to 3.6 V
• CY14E101J: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C101J/CY14B101J/CY14E101J combines a
1-Mbit nvSRAM[1] with a nonvolatile element in each memory
cell. The memory is organized as 128 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X101J1). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through I2C commands.
Configuration
Feature
AutoStore
Software
STORE
CY14X101J1
No
Yes
CY14X101J2
Yes
Yes
CY14X101J3
Yes
Yes
Low power consumption
Hardware
No
No
Yes
Average active current of 1 mA at 3.4 MHz operation
STORE
Average standby mode current of 150 uA
Sleep mode current of 8 uA
Logic Block Diagram
VCC VCAP
Serial Number
8x8
Manufacture ID/
Product ID
Power Control
Block
Sleep
Memory Control Register
Command Register
Quantrum Trap
128 K x 8
www.DataSSDheAet4U.com 2
SCL I C Control Logic
A2, A1
Slave Address
Decoder
WP
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
SRAM
128 K x 8
STORE
RECALL
Note
1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-54050 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2011
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CY14C101J Datasheet, Funktion
PRELIMINARY
CY14C101J
CY14B101J, CY14E101J
Acknowledge/No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data trans-
ferred on the I2C bus needs to be responded with an ACK signal
by the receiver to continue the operation. Failing to do so is
considered as a NACK state. NACK is the state where receiver
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE
operation in following cases:
nvSRAM did not receive valid data due to noise.
The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
The master did not receive valid data due to noise
Figure 6.
Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
SCL FROM
MASTER
S
START
condition
1
not acknowledge (A)
acknowledge (A)
2 89
clock pulse for
acknowledgement
High-Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 bit/s. A master code (0000 1XXXb) must be issued to place
the device into high speed mode. This enables master slave
communication for speed upto 3.4 MHz. A stop condition exits
Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
F/S-mode
Hs-mode
F/S-mode
S MASTER CODE A Sr SLAVE ADD. R/W A
DATA
A/A P
n (bytes+ack.)
Hs-mode continues
www.DataSheet4U.com
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
Sr SLAVE ADD.
continue data transfer in Hs-mode, the master sends Repeated
START (Sr). See Figure 13 on page 11 and Figure 16 on page
12 for Hs-mode timings for read and write operation.
Document #: 001-54050 Rev. *D
Page 6 of 32
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CY14C101J pdf, datenblatt
PRELIMINARY
CY14C101J
CY14B101J, CY14E101J
Figure 15. Current Location Single-Byte nvSRAM Read (except Hs-mode)
By Master
SDA Line
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 X 1
S
AT
0
P
P
By nvSRAM
Data Byte
A
Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 X 1
A
Data Byte
A
Data Byte N
Figure 17. Current Location Single-Byte nvSRAM Read (Hs-mode)
S
AT
0
P
P
By Master
SDA Line
S
T
A
R Hs-mode command
T
S00 0 01 XX X
Memory Slave Address
Sr 1 0 1 0 A2 A1 X 1
S
AT
0
P
P
By nvSRAM
A A Data Byte
Figure 18. Current Location Multi-Byte nvSRAM Read (Hs-mode)
By Master
SDA Line
S
T
A
R Hs-mode command
T
S00 0 01 XX X
Memory Slave Address
Sr 1 0 1 0 A2 A1 X 1
By nvSRAM
AA
Data Byte
A
Data Byte N
S
A
T
0
P
P
www.DataSheet4U.com
Document #: 001-54050 Rev. *D
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