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CY14B512Q3 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14B512Q3
Beschreibung 512-Kbit (64 K X 8) Serial (SPI) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 27 Seiten
CY14B512Q3 Datasheet, Funktion
CY14B512Q1
CY14B512Q2
CY14B512Q3
512-Kbit (64 K × 8) Serial (SPI) nvSRAM
Features512-Kbit (64 K × 8) Serial (SPI) nvSRAM
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14B512Q1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
High speed serial peripheral interface (SPI)
40 MHz clock rate
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4,1/2, or entire array
Low power consumption
Single 3 V +20%, –10% operation
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
Industrial temperature
CY14B512Q1 has identical pin configuration to industry
standard 8-pin NV memory
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B512Q1/CY14B512Q2/CY14B512Q3
combines a 512-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B512Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B512Q1
No
Yes
CY14B512Q2
Yes
Yes
CY14B512Q3
Yes
Yes
No No Yes
Logic Block Diagram
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
64 K X 8
SRAM Array
64 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
www.DataSheet4U.com
SI
Instruction
register
Address
Decoder
A0-A15
D0-D7
Data I/O register
SO
Note
1. This device will be referred to as nvSRAM throughout the document.
Status Register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-53873 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 12, 2011
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CY14B512Q3 Datasheet, Funktion
CY14B512Q1
CY14B512Q2
CY14B512Q3
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle was performed since the last RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Disable (ASDISB) Instruction on page 14.
If AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the data stored in the
nvSRAM and Status Register. To resume normal functionality,
the WRSR instruction must be issued to update the nonvolatile
bits BP0, BP1 and WPEN in the Status Register.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation.
Refer to DC Electrical Characteristics on page 16 for the size of
the VCAP.
Note CY14B512Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14B512Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM was performed
since the last STORE or RECALL cycle. Reads and writes to the
memory are inhibited for tSTORE duration or as long as HSB pin
is LOW.
wwwTh.DeaHtaSSBhepeint4Ual.scoomacts as an open drain driver (internal 100 kΩ
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 kΩ pull-up
resistor.
Note For successfull last data byte STORE, a hardware store
should be initiated atleast one clock cycle after the last data bit
D0 is recieved.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Note CY14B512Q1/CY14B512Q2 do not have HSB pin. RDY bit
of the SPI Status Register may be probed to determine the
Ready or Busy status of nvSRAM.
Figure 3. AutoStore Mode
VCC
0.1 uF
VCC
CS VCAP
VSS
VCAP
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Document #: 001-53873 Rev. *E
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CY14B512Q3 pdf, datenblatt
CY14B512Q1
CY14B512Q2
CY14B512Q3
Write Protect (WP) Pin
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This enables the user to install the device in a
system with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and block protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
CY14B512Q2 does not have WP pin and therefore does not
provide hardware write protection.
Table 7 summarizes all the protection features of this device
Table 7. Write Protection Operation
WPEN
X
0
1
WP
X
X
LOW
WEN
Protected
Blocks
Unprotected
Blocks
0 Protected Protected
1 Protected Writable
1 Protected Writable
Status
Register
Protected
Writable
Protected
1 HIGH 1 Protected Writable Writable
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) instruction
The read operations on this device are performed by giving the
instruction on the SI and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by two bytes
of address (A15-A0). After the last address bit is transmitted on
the SI pin, the data (D7-D0) at the specific address is shifted out
on the SO line on the falling edge of SCK starting with D7. Any
other data on SI line after the last address bit is ignored.
CY14B512Q1/CY14B512Q2/CY14B512Q3 allows reads to be
performed in bursts through SPI which can be used to read
consecutive addresses without issuing a new READ instruction.
If only one byte is to be read, the CS line must be driven HIGH
after one byte of data comes out. However, the read sequence
may be continued by holding the CS line LOW and the address
is automatically incremented and data continues to shift out on
SO pin. When the last data memory address (0xFFFF) is
reached, the address rolls over to 0x0000 and the device
continues to read.
Write Sequence (WRITE) instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is Write Disabled,
then the device must first be Write Enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by 2 bytes of address (A15-A0) and the data (D7-D0)
which is to be written.
CY14B512Q1/CY14B512Q2/CY14B512Q3 enables writes to be
performed in bursts through SPI which can be used to write
consecutive addresses without issuing a new WRITE instruction.
If only one byte is to be written, the CS line must be driven HIGH
after the D0 (LSB of data) is transmitted. However, if more bytes
are to be written, CS line must be held LOW and address is
incremented automatically. The following bytes on the SI line are
treated as data bytes and written in the successive addresses.
When the last data memory address (0xFFFF) is reached, the
address rolls over to 0x0000 and the device continues to write.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Figure 11. Read Instruction Timing
CS
SCK
0 1 2 34 5 67 0 1 23 45 6 7
12 13 14 15 0 1 2 3 4 5 6 7
Op-Code
16-bit Address
www.DataSShIeet4U.co0m 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8
MSB
HI-Z
SO
32
10
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Document #: 001-53873 Rev. *E
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