CY14B256Q3 Datasheet PDF - Cypress Semiconductor
| Part Number | CY14B256Q3 | |
| Description | 256-Kbit (32 K X 8) Serial (SPI) nvSRAM | |
| Manufacturers | Cypress Semiconductor | |
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CY14B256Q1
CY14B256Q2
CY14B256Q3
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
Features
■ 256-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 32 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14B256Q1)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ High-speed serial peripheral interface (SPI)
❐ 40-MHz clock rate
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4,1/2, or entire array
■ Low power consumption
❐ Single 3 V +20%, –10% operation
❐ Average active current of 10 mA at 40-MHz operation
Logic Block Diagram
■ Industry standard configurations
❐ Industrial temperature
❐ CY14B256Q1 has identical pin configuration to industry
standard 8-pin NV memory
❐ 8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B256Q1/CY14B256Q2/CY14B256Q3
combines a 256-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 32 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B256Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B256Q1
No
Yes
CY14B256Q2
Yes
Yes
No No
CY14B256Q3
Yes
Yes
Yes
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
32 K X 8
SRAM Array
32 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
www.DataSheet4U.com
SI
Instruction
register
Address
Decoder
A0-A14
D0-D7
Data I/O register
SO
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53882 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 24, 2011
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CY14B256Q1
CY14B256Q2
CY14B256Q3
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the ready status of the device.
Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
needs this setting to survive the power cycle, a STORE operation
must be performed following AutoStore Disable or Enable
operation.
Note CY14B256Q2/CY14B256Q3 has AutoStore enabled from
the factory. In CY14B256Q1, VCAP pin is not present and
AutoStore option is not available. The AutoStore Enable and
Disable instructions to CY14B256Q1 are ignored.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled in any case.
Noise Considerations
www.DataSheet4U.com
Refer to CY application note AN1064.
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with chip select (CS), serial input
(SI), serial output (SO), and serial clock (SCK) pins.
CY14B256Q1/CY14B256Q2/CY14B256Q3 provides serial
access to nvSRAM through SPI interface. The SPI bus on this
device can run at speeds up to 40 MHz.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are as follows:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the chip
select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14B256Q1/CY14B256Q2/CY14B256Q3 operates as a SPI
slave and may share the SPI bus with other SPI slave devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull-down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active chip
select cycle.
Document Number: 001-53882 Rev. *E
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