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CY14B256Q1 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14B256Q1
Beschreibung 256-Kbit (32 K X 8) Serial (SPI) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 26 Seiten
CY14B256Q1 Datasheet, Funktion
CY14B256Q1
CY14B256Q2
CY14B256Q3
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14B256Q1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
High-speed serial peripheral interface (SPI)
40-MHz clock rate
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4,1/2, or entire array
Low power consumption
Single 3 V +20%, –10% operation
Average active current of 10 mA at 40-MHz operation
Logic Block Diagram
Industry standard configurations
Industrial temperature
CY14B256Q1 has identical pin configuration to industry
standard 8-pin NV memory
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B256Q1/CY14B256Q2/CY14B256Q3
combines a 256-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 32 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B256Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B256Q1
No
Yes
CY14B256Q2
Yes
Yes
No No
CY14B256Q3
Yes
Yes
Yes
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
32 K X 8
SRAM Array
32 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
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SI
Instruction
register
Address
Decoder
A0-A14
D0-D7
Data I/O register
SO
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53882 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 24, 2011
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CY14B256Q1 Datasheet, Funktion
CY14B256Q1
CY14B256Q2
CY14B256Q3
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14B256Q1/CY14B256Q2/CY14B256Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of the first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.
Data Transmission - SI and SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14B256Q1/CY14B256Q2/CY14B256Q3 has two separate
pins for SI and SO, which can be connected with the master as
shown in Figure 2 on page 6.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
most significant bit (MSB). This is valid for both address and data
transmission.
The 256-Kbit serial nvSRAM requires a 2-byte address for any
read or write operation. However, since the address is only
15-bits, it implies that the first MSB that is fed in is ignored by the
device. Although this bit is ‘don’t care’, Cypress recommends
that this bit is treated as 0 to enable seamless transition to higher
memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14B256Q1/CY14B256Q2/CY14B256Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. Refer to Table 2 on page 8 for details.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
Status Register
CY14B256Q1/CY14B256Q2/CY14B256Q3 has an 8-bit Status
Register. The bits in the Status Register are used to configure
the SPI bus. These bits are described in the Table 4 on page 9.
Figure 2. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
CS1
HOLD1
CS2
HOLD2
SCK SI
SO
CY14B256Qx
CS HOLD
SCK SI
SO
CY14B256Qx
CS HOLD
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Document Number: 001-53882 Rev. *E
Page 6 of 26
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CY14B256Q1 pdf, datenblatt
CY14B256Q1
CY14B256Q2
CY14B256Q3
CS
SCK
SI
SO
Figure 10. Burst Mode Read Instruction Timing
01 2 3 456 7 01 2 3 45 6 7
12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7
Op-Code
15-bit Address
0 0 0 0 0 0 1 1 X 14 13 12 11 10 9 8
MSB
321 0
LSB
Data Byte 1
Data Byte N
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
Figure 11. Write Instruction Timing
CS
SCK
SI
SO
0 1 2 34 5 67 0 1 23 4 56 7
12 13 14 15 0 1 2 3 4 5 6 7
Op-Code
15-bit Address
0 0 0 0 0 0 1 0 X 14 13 12 11 10 9 8
MSB
3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
Data
LSB
HI-Z
Figure 12. Burst Mode Write Instruction Timing
CS
SCK
SI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7
Data Byte 1
Data Byte N
Op-Code
15-bit Address
0 0 0 0 0 0 1 0 X 14 13 12 11 10 9 8
MSB
3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
LSB
SO
nvSRAM Special Instructions
HI-Z
CY14B256Q1/CY14B256Q2/CY14B256Q3 provides four
special instructions which enables access to the nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
wwwTa.Dblaeta7Slhisetestt4hUe.sceominstructions.
Software STORE (STORE) instruction
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
Table 7. nvSRAM Special Instructions
Function Name
STORE
RECALL
ASENB
ASDISB
Opcode
0011 1100
0110 0000
0101 1001
0001 1001
Operation
Software STORE
Software RECALL
AutoStore Enable
AutoStore Disable
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Document Number: 001-53882 Rev. *E
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