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CY14B104NA Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14B104NA
Beschreibung 4-Mbit (512 K X 8/256 K X 16) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 24 Seiten
CY14B104NA Datasheet, Funktion
CY14B104LA, CY14B104NA
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
20 ns, 25 ns, and 45 ns access times
Internally organized as 512 K × 8 (CY14B104LA) or 256 K ×
16 (CY14B104NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20%, -10% operation
Industrial temperature
Packages
44-/54-pin thin small outline package (TSOP II)
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 512 K bytes of 8 bits each or 256 K
words of 16 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram[1, 2, 3]
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Notes
1. Address A0 - A18 for ×8 configuration and Address A0 - A17 for ×16 configuration.
2. Data DQ0 - DQ7 for ×8 configuration and Data DQ0 - DQ15 for ×16 configuration.
3. BHE and BLE are applicable for ×16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-49918 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2011
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CY14B104NA Datasheet, Funktion
CY14B104LA, CY14B104NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104LA/CY14B104NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B104LA/CY14B104NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on powerup, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B104LA/CY14B104NA
software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
Table 2. Mode Selection
CE WE OE BHE, BLE[9]
H X XX
L H LL
L L XL
L H LX
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1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
A15 - A0[10]
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Mode
Not selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
I/O
Output high-Z
Output data
Input data
Output data
Output data
Output data
Output data
Output data
Output data
Power
Standby
Active
Active
Active[11]
Notes
9. BHE and BLE are applicable for x16 configuration only.
10.
While there are 19 address lines
The remaining address lines are
on the CY14B104LA
don’t care.
(18
address
lines
on
the
CY14B104NA),
only
13
address
lines
(A14
-
A2)
are
used
to
control
software
modes.
11. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-49918 Rev. *H
Page 6 of 24
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CY14B104NA pdf, datenblatt
CY14B104LA, CY14B104NA
Figure 7. SRAM Read Cycle #2: CE and OE Controlled[21, 22, 23]
Address
CE
OE
BHE, BLE
Data Output
High Impedance
ICC Standby
Address Valid
tACE
tRC
tAA
tLZCE
tLZOE
tDOE
tDBE
tLZBE
tPU
Active
tHZCE
tHZOE
tHZBE
Output Data Valid
tPD
Address
CE
BHE, BLE
WE
Data Input
Data Output
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Figure 8. SRAM Write Cycle #1: WE Controlled[21, 23, 24, 25]
tWC
Address Valid
tSCE
tHA
tSA
Previous Data
tBW
tAW
tPWE
tHZWE
tSD tHD
Input Data Valid
tLZWE
High Impedance
Notes
21. BHE and BLE are applicable for ×16 configuration only.
22. WE must be HIGH during SRAM read cycles.
23. HSB must remain HIGH during read and write cycles.
24. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
25. CE or WE must be >VIH during address transitions.
Document #: 001-49918 Rev. *H
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