PDF ADF7241 Data sheet ( Hoja de datos )

Número de pieza	ADF7241
Descripción	Low Power IEEE 802.15.4 Zero-IF 2.4 GHz Transceiver IC
Fabricantes	Analog Devices
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Low Power IEEE 802.15.4 Zero-IF 2.4 GHz Transceiver IC ADF7241 FEATURES Frequency range (global ISM band) 2400 MHz to 2483.5 MHz IEEE 802.15.4-2006-compatible (250 kbps) Low power consumption 19 mA (typical) in receive mode 21.5 mA (typical) in transmit mode (PO = 3 dBm) 1.7 μA, 32 kHz crystal oscillator wake-up mode High sensitivity −95 dBm at 250 kbps Programmable output power −20 dBm to +4.8 dBm in 2 dB steps Integrated voltage regulators 1.8 V to 3.6 V input voltage range Excellent receiver selectivity and blocking resilience Zero-IF architecture Complies with EN300 440 Class 2, EN300 328, FCC CFR47 Part 15, ARIB STD-T66 Digital RSSI measurement Fast automatic VCO calibration Automatic RF synthesizer bandwidth optimization On-chip low power processor performs Radio control Packet management Packet management support Insertion/detection of preamble address/SFD/FCS IEEEE 802.15.4-2006 frame filtering IEEEE 802.15.4-2006 CSMA/CA unslotted modes Flexible 256-byte transmit/receive data buffer SPORT mode Flexible multiple RF port interface External PA/LNA support hardware Switched antenna diversity support Wake-up timer Very few external components Integrated PLL loop filter, receive/transmit switch, battery monitor, temperature sensor, 32 kHz RC and crystal oscillators Flexible SPI control interface with block read/write access Small form factor 5 mm × 5 mm 32-lead LFCSP package APPLICATIONS Wireless sensor networks Automatic meter reading/smart metering Industrial wireless control Healthcare Wireless audio/video Consumer electronics ZigBee ADF7241 LNA1 LNA2 FUNCTIONAL BLOCK DIAGRAM DAC ADC ADC DAC DSSS DEMOD AGC OCL CDR 8-BIT PROCESSOR RADIO CONTROLLER PACKET MANAGER www.DataSheet4U.com PA LDO × 4 FRACTIONAL-N RF SYNTHESIZER PRE-EMPHASIS FILTER WAKE-UP CTRL BIAS BATTERY TEMPERATURE MONITOR SENSOR 26MHz OSC 32kHz RC OSC 32kHz XTAL OSC 4kB PROGRAM ROM 2kB PROGRAM RAM 256-BYTE PACKET RAM 64-BYTE BBRAM 256-BYTE MCR SPI GPIO SPORT IRQ Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. 1 page ADF7241 SPECIFICATIONS VDD_BAT = 1.8 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD_BAT = 3.6 V, TA = 25°C, fCHANNEL = 2450 MHz. All measurements are performed using the ADF7241 reference design, RFIO2 port, unless otherwise noted. GENERAL SPECIFICATIONS Table 1. Parameter GENERAL PARAMETERS Voltage Supply Range VDD_BAT Input Frequency Range Operating Temperature Range Data Rate Min Typ Max Unit Test Conditions 1.8 2400 −40 250 3.6 2483.5 +85 V MHz °C kbps RF FREQUENCY SYNTHESIZER SPECIFICATIONS Table 2. Parameter CHANNEL FREQUENCY RESOLUTION PHASE ERROR Min Typ 10 3 Max 1.5 VCO CALIBRATION TIME SYNTHESIZER SETTLING TIME 52 PHASE NOISE REFERENCE AND CLOCK-RELATED SPURIOUS INTEGER BOUNDARY SPURS 53 80 −135 −145 70 60 CRYSTAL OSCILLATOR Crystal Frequency Maximum Parallel Load Capacitance Minimum Parallel Load Capacitance Maximum Crystal ESR Sleep-to-Idle Wake-Up Time 26 18 7 365.3 300 Unit kHz Degrees Degrees μs μs μs dBc/Hz dBc/Hz dBc dBc Test Conditions Receive mode; integration bandwidth from 10 kHz to 400 kHz Transmit mode; integration bandwidth from 10 kHz to 1800 kHz Applies to all modes Frequency synthesizer settled to <±5 ppm of the target frequency within this time following a VCO calibration Receive mode Transmit mode Receive mode 10 MHz frequency offset ≥50 MHz frequency offset Receive mode; fCHANNEL = 2405 MHz, 2450 MHz, and 2480 MHz Receive mode; measured at 400 kHz offset from fCHANNEL = 2405 MHz, 2418 MHz, 2431 MHz, 2444 MHz, 2457 MHz, 2470 MHz MHz Parallel load resonant crystal pF pF Ω Guarantees maximum crystal frequency error of 0.2 ppm; 33 pF on XOSC26P and XOSC26N μs 15 pF load on XOSC26N and XOSC26P www.DataSheet4U.com Rev. 0 \| Page 5 of 72 5 Page TIMING DIAGRAMS SPI Interface Timing Diagram CS t2 t3 t4 t5 SCLK t11 t9 t10 MISO t1 BIT 7 t6 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 0 X t8 t7 MOSI 765432107 Figure 3. SPI Interface Timing Additional description and timing diagrams are available in the Serial Peripheral interface section. Sleep-to-Idle SPI Timing Diagrams ADF7241 BIT 7 7 CS SCLK MISO t12 t1 t9 76543210 t6 X Figure 4. Sleep-to-Idle State Timing t16 CS SPI COMMAND TO ADF7242 RC_RESET OR RC_SLEEP DEVICE STATUS IDLE, PHY_RDY, RX SLEEP IDLE Figure 5. Wake-Up After an RC_RESET or RC_SLEEP Command www.DataSheet4U.com Rev. 0 \| Page 11 of 72 11 Page

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