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PDF MC68HC55 Data sheet ( Hoja de datos )
| Número de pieza | MC68HC55 | |
| Descripción | Two-Channel CMOS ASIC Device | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Order Number: MC68HC55
Rev. 2
MC68HC55/D
Technical Data
Two-Channel CMOS ASIC Device
www.DataSheet4U.com
Section 1. DSI/D (Distributed System Interface – Digital)
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.2 General Description of the DSI System. . . . . . . . . . . . . . . . .3
1.3 Overall DSI System Connections . . . . . . . . . . . . . . . . . . . . .3
Section 2. MC68HC55CD Pin Assignments and Descriptions
2.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Section 3. Registers and Bit Descriptions
3.1 DSI Channel 0 Data Registers . . . . . . . . . . . . . . . . . . . . . . .9
3.2 DSI Channel 1 Data Registers . . . . . . . . . . . . . . . . . . . . . .10
3.3 DSI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 DSI Channel Control Registers . . . . . . . . . . . . . . . . . . . . . .13
3.5 DSI Channel Enable Bits. . . . . . . . . . . . . . . . . . . . . . . . . . .17
Section 4. Functional Description
4.1 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Abort Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3 Enable (Disable) Function . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4 SPI Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.5 DSI/D to DSI/P Communications. . . . . . . . . . . . . . . . . . . . .29
4.6 CRC Generation/Checking . . . . . . . . . . . . . . . . . . . . . . . . .30
4.7 CRC Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.8 Message Size Special Cases . . . . . . . . . . . . . . . . . . . . . . .31
Section 5. Timing and Electrical Specifications
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.2 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . .34
5.3 Timing Characteristics for DSI/D to DSI/P Interface . . . . . .34
5.4 Timing Characteristics for SPI Interface . . . . . . . . . . . . . . .36
Section 6. Mechanical Data and Ordering Information
6.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.2 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 1999, 2006
1 page  
MC68HC55 Technical Data
Pin Assignments
The second message assigns the address to the second node and
receives a response message from the first node at the same time. The
first node ignores the second address assignment message because it
already has an address. During the third address assignmewnwt wm.DesatsaaShgeeet,4U.com
only the second node responds (a node only responds to the assignment
message once).This sequence continues until all nodes have been
assigned addresses and have responded that the assignment was
successful.
Now that the nodes each have a unique address, messages can be sent
and received from individual nodes. Notice that during a message, the
node that is receiving the command and the node that is returning a
response are not necessarily the same node.
Nodes do not have any permanently programmed address. Addresses
are assigned according to the order of the devices on the bus every time
power is applied. Multiple nodes may be replaced and/or the system can
be reconfigured by adding nodes to the bus, and the system will
automatically reconfigure itself at the next power-on.
Section 2. MC68HC55CD Pin Assignments and Descriptions
Refer to Figure 2-1 for the MC68HC55CD pin assignments. A brief
description of the pins is given in this section.
2.1 Pin Assignments
SCLK
CLK
DI
DO
CS
RESET
INT
GND
1
2
3
4
5
6
7
8
16 VDD
15 DSI0F
14 DSI0S
13 DSI0R
12 N/C
11 DSI1F
10 DSI1S
9 DSI1R
16-lead narrow body SOIC, package #751B-05 issue J
Figure 2-1. MC68HC55CD Pin Assignments
MC68HC55
MC68HC55CD Pin Assignments and Descriptions
Technical Data
5
5 Page 
MC68HC55 Technical Data
DSI Status Register
NOTE:
visible via the SPI until chip select rises and returns low to start a new
SPI transfer. Reads of this register should be considered a snapshot of
the status at the last falling edge of chip select.
To guarantee coherence between an SPI read of status anwdwdwa.Dtaat,atShheeet4U.com
reads must be within the same SPI burst (CS must remain continuously
low for the data and status reads). One way to assure this is to always
read data in a burst, starting with a command referencing DSI0H through
DSI1L, leaving the register pointer pointing at the DSISTAT register (see
Figure 4-7). The first SPI transfer which corresponds to the read or write
address 000 command will return (read) register 100 (DSISTAT). The
values of DSISTAT and DSI0H through DSI1L are latched at the falling
edge of CS, so changes due to DSI transfers are not seen until a future
SPI transfer.
ER1 — CRC Error Bit (Channel 1 Read)
0 = CRC value for the data in the read buffer was correct.
1 = CRC value for the data in the read buffer was not correct (data
is not valid).
CRC errors are associated with each data value in the receive FIFO,
so each FIFO entry has a bit to indicate whether the data in that stage
of the FIFO was received correctly.
Whenever a received value is visible at DSI1H:DSI1L, the associated
CRC error status is visible at ER1 in the DSISTAT register. When a
new data value becomes visible due to a pop of a previous value, the
ER1 status flag reflects the CRC status of the new data value. There
is no separate interrupt associated with ER1 because it is always
associated with the RFNE1 status flag.
TFE1 — Transmit FIFO Empty Bit (Channel 1)
0 = Transmit FIFO not empty
1 = Transmit FIFO empty
When the transmit FIFO is empty, four consecutive write bursts may
be used to fill the FIFO without checking the flags between writes. An
interrupt may be generated on the transmit FIFO empty condition.
MC68HC55
Registers and Bit Descriptions
Technical Data
11
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