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PDF MC68HC16Y1 Data sheet ( Hoja de datos )

Número de pieza MC68HC16Y1
Descripción 16-Bit Modular Microcontroller
Fabricantes Freescale Semiconductor 
Logotipo Freescale Semiconductor Logotipo



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MOTOROLA
Freescale Semiconductor, Inc. Order this document
SEMICONDUCTOR
by MC68HC16Y1TS/D Rev. 1
TECHNICAL DATA
MC68HC16Y1
Technical Summary
16-Bit Modular Microcontroller
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1 Introduction
The MC68HC16Y1 is a high-speed 16-bit control unit that is upwardly code compatible with M68HC11
controllers. It is a member of the M68300/68HC16 Family of modular microcontrollers.
M68HC16 controllers are built up from standard modules that interface via a common internal bus.
Standardization facilitates rapid development of devices tailored for specific applications.
The MC68HC16Y1 incorporates a true 16-bit CPU (CPU16), a single-chip integration module (SCIM),
an 8/10-bit analog-to-digital converter (ADC), a multichannel communication interface (MCCI), a gen-
eral-purpose timer (GPT), a time processing unit (TPU), a 2 Kbyte standby RAM module with TPU ROM
emulation capability (TPURAM), and a 48 Kbyte masked ROM module (MRM). These modules are in-
terconnected by the Motorola intermodule bus (IMB).
The MC68HC16Y1 can either synthesize an internal clock signal from an external reference, or use an
external clock input directly. Operation with a 32.768 kHz reference frequency is standard, but operation
with a 4.0 MHz reference is available as an option — contact your Motorola representative for more in-
formation. System hardware and software allow changes in clock rate during operation. Because the
MC68HC16Y1 is a fully static design, register and memory contents are not affected by clock rate
changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power
consumption of the MC68HC16Y1 low. Power consumption can be minimized by stopping the system
clock. The M68HC16 instruction set includes a low-power stop (LPSTOP) command that efficiently im-
plements this capability.
Package Type
Plastic Surface Mount
FC Suffix
Table 1 Ordering Information
Frequency (MHz)
16.78
Temperature
–40° to +85°C
Order Number
M68HC16Y1CFC
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1992, 1996 For More Information On This Product,
Go to: www.freescale.com

1 page




MC68HC16Y1 pdf
Freescale Semiconductor, Inc.
1
VRH
AN5
AN4
AN3
AN2
AN1
AN0
VSSA
VDDA
VDDE
VSSE
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
VSSI
ADDR10
ADDR11
ADDR12
ADDR13
VDDE
VSSE
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
SS
MOSI
MISO
SCK
TXDA
RXDA
TXDB
VDDE
40
2
3
4
5
6
7
8
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10
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12
13
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15
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31
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MC68HC16Y1
Figure 2 MC68HC16Y1 160-Pin QFP Pinout
120
VDDE
119 DATA0
118 wDwATwA1.DataSheet4U.com
117 DATA2
116 DATA3
115 DATA4
114 DATA5
113 DATA6
112 DATA7
111 DATA8
110 DATA9
109 DATA10
108 VDDE
107 VSSE
106 DATA11
105 DATA12
104 DATA13
103 DATA14
102 DATA15
101 VSSI
100 ADDR0
99 DSACK0
98 DSACK1
97 AVEC
96 PE3
95 VDDE
94 VSSE
93 DS
92 AS
91 SIZ0
90 SIZ1
89 R/W
88 MODCLK
87 IRQ1
86 IRQ2
85 IRQ3
84 IRQ4
83 IRQ5
82 IRQ6
IRQ7
81
Y1 160-PIN QFP
MC68HC16Y1
MC68HC16Y1TS/D
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5

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MC68HC16Y1 arduino
Freescale Semiconductor, Inc.
2.4 Condition Code Register
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
S MV H EV N Z V C
INT SM
PK
The condition code register can be considered as two functional blocks. The MSB, which corresponds
to the CCR in the M68HC11, contains the low-power stop control bit and processor status flags. The
LSB contains the interrupt priority field, the DSP saturation mode control bit, and the program counter
address extension field.
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S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed.
1 = Perform NOP when LPSTOP instruction is executed.
MV — Accumulator M overflow flag
Set when overflow into the accumulator M sign bit (AM35) has occurred.
H — Half Carry Flag
Set when a carry from bit 3 in accumulators A or B occurs during BCD addition.
EV — Extension Bit Overflow Flag
Set when an overflow into bit 31 of accumulator M has occurred.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when twos complement overflow occurs as the result of an operation.
C — Carry Flag
Set when a carry or borrow occurs during arithmetic operation. Also used during shift and rotate oper-
ations to facilitate multiple word operations.
INT[2:0] — Interrupt Priority Mask
The value of this field ($0 to $7) specifies the CPU16 interrupt priority level.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from accumulator M using TMRT or TMET will be
given maximum positive or negative value, depending on the state of the AM sign bit before overflow.
PK[3:0] — Program Counter Address Extension Field
This field is concatenated with the program counter to form a 20-bit pseudolinear address.
MC68HC16Y1
MC68HC16Y1TS/D
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
11

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