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PDF LR070BA016 Data sheet ( Hoja de datos )

Número de pieza LR070BA016
Descripción 7.0 TFT LCD Module
Fabricantes Chilin 
Logotipo Chilin Logotipo



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CHI LIN TECHNOLOGY CO., LTD.
Product Specifications
Customer
Description
7.0” TFT LCD Module
Model Name
LR070BA016
Date
2007/03/19
Doc. No.
Revision
00
Customer Approval
Date
The above signature represents that the product specifications, testing regulation, and
warranty in the specifications are accepted
Check
Engineering
Date
Prepared
Date
Head Office & Factory : No. 71, Te Lun Rd., Jen Te Hsiang, Tainan County 717, Taiwan,
R.O.C.
Tel : +886-6-279-4113
Fax: +886-6-279-1194
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LR070BA016 pdf
4Interface (Input terminal)
4.1. TFT-LCD Panel Driving Part
Pin No. SYMBOL I/O FUNCTION
1
GND
- Ground for logic circuit
2
VCC
I Supply voltage for logic control circuit
3 VGL I Negative power for scan driver
4
VGH
I Positive power for scan driver
5 STVR I/O Vertical start pulse
6 STVL I/O Vertical start pulse
7 CKV I Shift clock input for scan driver
8 U/D
I UP/DOWN scan control input
9
OEV
I Output enable input for scan driver
10 VCOM I Common electrode driving signal
11 VCOM I Common electrode driving signal
12 L/R
I LEFT/RIGHT scan control input
13 MOD I Analog signal rotate input
14 OEH
I Output enable input for data driver
15 STHL I/O Start pulse for horizontal scan line
16 STHR I/O Start pulse for horizontal scan line
17 CPH3 I Sampling and shifting clock pulse for data driver
18 CPH2 I Sampling and shifting clock pulse for data driver
19 CHP1 I Sampling and shifting clock pulse for data driver
20 VCC
I Supply voltage of logic control circuit
21 GND
- Ground for logic circuit
22 VR
I Alternated video signal input (Red)
23 VG
I Alternated video signal input (Green)
24 VB
I Alternated video signal input (Blue)
25 AVDD I Supply voltage for analog circuit
26 AVSS - Ground for analog circuit
Doc. No.
REMARK
Rev. : 00
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Date : 2007/03/19

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LR070BA016 arduino
6.4. Sampling Mode Change
SEQ/SIM
H ( High Level )
MOD
Simultaneous Sampling Mode
Doc. No.
L ( Low Level )
Sequential Sampling Mode
„ Timing Diagram
Tcph
Tcwh
CPH1
CPH2
70%
Tc12
70%
70%
70%
70%
Tc23
Tc31
CPH3
70%
VA
STHin
Tasu Tahd
70%
70%
VA(1'st)
VA(2'nd)
Tsu Thd
70% 70%
STHout
70%
70%
Tphl
Tphl
70% 70%
STHin
OE
(EDGSL = "L")
OE
(EDGSL = "H")
QAn , QBn
QCn
Twoe
30%
Tdis
30%
70%
70%
30%
Tst 96%
Twoe
30%
Tdis
30%
70%
70%
30%
Tst 96%
Rev. : 00
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Date : 2007/03/19

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