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PDF CY7C64315 Data sheet ( Hoja de datos )
| Número de pieza | CY7C64315 | |
| Descripción | (CY7C6431X - CY7C6435X) enCoRe V Full Speed USB Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C6431x
CY7C6434x, CY7C6435x
enCoRe™ V Full Speed USB Controller
Features
■ Powerful Harvard Architecture Processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 3.0V to 5.5V operating voltage without USB
❐ Operating voltage with USB enabled:
• 3.15V to 3.45V when supply voltage is around 3.3V
• 4.35V to 5.25V when supply voltage is around 5.0V
❐ Commercial temperature range: 0°C to +70°C
❐ Industrial temperature range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ Up to 32K Flash program storage:
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-System Serial Programming (ISSP)
■ Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K trace memory
■ Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator:
• 0.25% accuracy with Oscillator Lock to USB data, no
external components required
• Internal low speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
■ Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ 25 mA sink current on all GPIO
❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current
❐ Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8V
❐ Selectable, regulated digital I/O on Port 1
❐ Configurable input threshold for Port 1
❐ Hot-swappable Capability on Port 1
■ Full-Speed USB (12 Mbps)
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 512 bytes buffer
❐ No external crystal required
■ Additional System Resources
❐ Configurable communication speeds
❐ I2C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 μA
• Hardware address detection
❐ SPI master and SPI slave:
• Configurable between 46.9 kHz and 12 MHz
❐ Three 16-bit timers
❐ 10-bit ADC used to monitor battery voltage or other signals
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
enCoRe V Block Diagram
enCoRe V
CORE
SRAM
2048 Bytes
Interrupt
Controller
Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO
SROM
8K/16K/32K Flash
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
System Bus
Sleep and
Watchdog
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Full
Speed
USB
SYSTEM RESOURCES
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12394 Rev *I
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2009
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1 page  
CY7C6431x
CY7C6434x, CY7C6435x
Additional System Resources
System resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. The following statements describe the merits of each
system resource.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (power
on reset) circuit eliminates the need for a system supervisor.
■ The 5V maximum input, 1.8, 2.5, or 3V selectable output, low
dropout regulator (LDO) provides regulation for I/Os. A register
controlled bypass mode enables the user to disable the LDO.
■ Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V family of parts.
Getting Started
The quickest path to understanding the enCoRe V silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the enCoRe V integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC Programmable System-on-Chip Technical Reference
Manual, which can be found on http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest enCoRe V device data sheets
on the web at http://www.cypress.com.
Development Kits
Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark. Under
Product Categories, click USB (Universal Serial Bus) to view a
current list of available items.
Technical Training Modules
Free technical training (on demand, webinars, and workshops)
is available online at www.cypress.com/training. The training
covers a wide variety of topics and skill levels to assist you in
your designs.
Consultants
Certified USB consultants offer everything from technical assis-
tance to completed PSoC designs. To contact or become a PSoC
Consultant go to www.cypress.com/cypros.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Document Number: 001-12394 Rev *I
www.DataSheet.in
Page 5 of 32
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5 Page 
48-Pin Part Pinout
CY7C6431x
CY7C6434x, CY7C6435x
Figure 8. CY7C64355/CY7C64356 48-Pin enCoRe V USB Device
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36 P2[6]
35 P2[4]
34 P2[2]
33 P2[0]
32 P4[2]
31 P4[0]
30 P3[6]
29 P3[4]
28 P3[2]
27 P3[0]
26 XRES
25 P1[6]
Table 3. 48-Pin Part Pinout (QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Type
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
NC
NC
IOHR
IOHR
Power
I/O
I/O
Power
IOHR
IOHR
IOHR
IOHR
Pin Name
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
NC
P1[3]
P1[1](1, 2)
Vss
D+
D–
Vdd
P1[0](1, 2)
P1[2]
P1[4]
P1[6]
Description
No connection
Digital I/O
Digital I/O, Crystal Out (Xout)
Digital I/O, Crystal In (Xin)
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O, I2C SCL, SPI SS
Digital I/O, I2C SDA, SPI MISO
No connection
No connection
Digital I/O, SPI CLK
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Supply ground
USB
USB
Supply voltage
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
Digital I/O,
Digital I/O, optional external clock input (EXTCLK)
Digital I/O
Document Number: 001-12394 Rev *I
www.DataSheet.in
Page 11 of 32
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| PDF Descargar | [ Datasheet CY7C64315.PDF ] | |
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