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PDF 26DF161 Data sheet ( Hoja de datos )
| Número de pieza | 26DF161 | |
| Descripción | AT26DF161 | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 66 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
– Sixteen 128-Kbyte Physical Sectors
• Hardware Controlled Locking of Protected Sectors
• Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 4 µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (200-mil wide)
1. Description
The AT26DF161 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT26DF161, with its erase granularity as small as 4-Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF161 have been opti-
mized to meet the needs of today's code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
16-megabit
2.7-volt Only
Serial Firmware
DataFlash®
Memory
AT26DF161
For New
Designs Use
AT25DF161
3599H–DFLASH–8/09
1 page  
AT26DF161
5. Device Operation
The AT26DF161 is controlled by a set of instructions that are sent from a host controller, com-
monly referred to as the SPI Master. The SPI Master communicates with the AT26DF161 via the
SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26DF161 supports the two most common modes, SPI
Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.
Following the opcode, instruction dependent information such as address and data bytes would
then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with
the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT26DF161 will be ignored by the device and no operation will be
started. The device will continue to ignore any data presented on the SI pin until the start of the
next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-
serted before complete opcode and address information is sent to the device, then no operation
will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23-A0. Since the upper address limit of the AT26DF161 memory array is
1FFFFFh, address bits A23-A21 are always ignored by the device.
3599H–DFLASH–8/09
5
5 Page 
AT26DF161
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erasing algorithm that can detect when a byte loca-
tion fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the
Status Register.
Figure 8-4. Chip Erase
CS
SCK
SI
SO
01234567
OPCODE
CCCCCCCC
MSB
HIGH-IMPEDANCE
9. Protection Commands and Features
9.1 Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis-
ter to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector,
Unprotect Sector, or Write Status Register command can be executed. This makes the issuance
of these commands a two step process, thereby reducing the chances of a command being
accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the
issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be set to a logical “1”. The complete opcode must be clocked into the
device before the CS pin is deasserted; otherwise, the device will abort the operation and the
state of the WEL bit will not change.
Figure 9-1. Write Enable
CS
SCK
SI
SO
01234567
OPCODE
00000110
MSB
HIGH-IMPEDANCE
3599H–DFLASH–8/09
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 26DF161.PDF ] | |
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