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TSC80C31 Schematic ( PDF Datasheet ) - TEMIC Semiconductors

Teilenummer TSC80C31
Beschreibung (TSC80C31 / TSC80C51) CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
Hersteller TEMIC Semiconductors
Logo TEMIC Semiconductors Logo 



Gesamt 19 Seiten
		
TSC80C31 Datasheet, Funktion
TSC80C31/80C51
CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
Description
The TSC80C31/80C51 is high performance SCMOS
versions of the 8051 NMOS single chip 8 bit µC.
The fully static design of the TSC80C31/80C51 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC80C31/80C51 retains all the features of the 8051
: 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ;
two 16 bit timers ; a 5-source, 2-level interrupt structure
; a full duplex serial port ; and on-chip oscillator and clock
circuits.
In addition, the TSC80C31/80C51 has two
software-selectable modes of reduced activity for further
reduction in power consumption. In the Idle Mode the
CPU is frozen while the RAM, the timers, the serial port,
and the interrupt system continue to function. In the
Power Down Mode the RAM is saved and all other
functions are inoperative.
The TSC80C31/80C51 is manufactured using SCMOS
process which allows them to run from 0 up to 44 MHz
with VCC = 5 V. The TSC80C31/80C51 is also available
at 20 MHz with 2.7 V < Vcc < 5.5 V.
D TSC80C31/80C51-L16 : Low power version
Vcc : 2.7–5.5 V Freq : 0–16 MHz
D TSC80C31/80C51-L20 : Low power version
Vcc : 2.7–5.5 V Freq : 0–20 MHz
D TSC80C31/80C51-12 : 0 to 12 MHz
D TSC80C31/80C51-20 : 0 to 20 MHz
D TSC80C31/80C51-25 : 0 to 25 MHz
D TSC80C31/80C51-30 : 0 to 30 MHz
D TSC80C31/80C51-36 : 0 to 36 MHz
D TSC80C31/80C51-40 : 0 to 40 MHz
D TSC80C31/80C51-44 : 0 to 44 MHz*
* Commercial and Industrial temperature range only. For other speed
and range please consult your sale office.
Features
D Power control modes
D 128 bytes of RAM
D 4 K bytes of ROM (TSC80C31/80C51)
D 32 programmable I/O lines
D Two 16 bit timer/counter
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8 µm CMOS process
D Boolean processor
D 5 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive and
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev. E (14 Jan.97)
www.DataSheet.in
1






TSC80C31 Datasheet, Funktion
TSC80C31/80C51
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
Power Down Mode
The instruction that sets PCON.1 is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The hardware reset initiates the Special Fucntion
Register. In the Power Down mode, VCC may be lowered
to mi-nimize circuit power consumption. Care must be
taken to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which freezes the
oscillator. Reset should not be released until the oscillator
has restarted and stabilized. A hardware reset is the only
way of exiting the power down mode.
Table 1 describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the data is a 1, the port
pin is held high during the power down mode by the
strong pullup, T1, shown in Figure 4.
Table 1. Status of the external pins during idle and power down modes.
MODE
Idle
Idle
Power Down
Power Down
PROGRAM MEMORY
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Port Data
Floating
Port Data
Floating
PORT1
Port Data
Port Data
Port Data
Port Data
PORT2
Port Data
Address
Port Data
Port Data
PORT3
Port Data
Port Data
Port Data
Port Data
Stop Clock Mode
Due to static design, the TSC80C31/80C51 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Figure 4. I/O Buffers in the TSC80C31/80C51 (Ports
1, 2, 3).
I/O Ports
The I/O buffers for Ports 1, 2 and 3 are implemented as
shown in Figure 4.
6
www.DataSheet.in
MATRA MHS
Rev. E (14 Jan.97)

6 Page







TSC80C31 pdf, datenblatt
TSC80C31/80C51
Absolute Maximum Ratings*
Ambient Temperature Under Bias :
C = Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I = Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Characteristics : Low Power Version
* Notice
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
TA = 0°C to 70°C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 20 MHz
TA = –40°C to 85°C ; Vcc = 2.7 V to 5.5 V ; F = 0 to 20 MHz
Symbol
Parameter
VIL Input Low Voltage
VIH Input High Voltage (Except XTAL and RST)
VIH2 Input High Voltage to RST for Reset
VIH1 Input High Voltage to XTAL1
VPD Power Down Voltage to Vcc in PD Mode
VOL Output Low Voltage (Ports 1, 2, 3) (4)
VOL1 Output Low Voltage Port 0, ALE, PSEN (4)
VOH Output High Voltage (Port 1, 2 and 3)
VOH1 Output High Voltage (Port 0 in External Bus Mode),
ALE, PSEN
IIL Logical 0 Input Current Ports 1, 2, 3
ILI Input Leakage Current
ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3)
IPD Power Down Current
RRST RST Pulldown Resistor
CIO Capacitance of I/O Buffer
Min Typ (3) Max Unit Test Conditions
– 0.5
0.2 VCC + 0.9
0.7 VCC
0.7 VCC
2.0
0.2 VCC – 0.1
VCC + 0.5
VCC + 0.5
VCC + 0.5
5.5
V
V
V
V
V
0.45 V IOL = 0.8 mA (2)
0.45 V IOL = 1.6 mA (2)
0.9 Vcc
V IOH = – 10 µA
0.9 Vcc
V IOH = – 40 µA
– 50 µA Vin = 0.45 V
± 10
– 650
µA 0.45 < Vin < VCC
µA Vin = 2.0 V
5 30 µA VCC = 2.0 V to 5.5 V
(1)
50 90 200 k
10 pF fc = 1 MHz, TA = 25_C
Icc (mA)
Operating (1)
Frequency/Vcc
2.7 V
3V
3.3 V
Max Typ Max Typ Max Typ
1 MHz
0.8 0.37 1 0.42 1.1 0.46
6 MHz
4 2.2 5 2.5 6 2.7
12 MHz
8 4 10 4.7 12 5.3
16 MHz
10 5 12 5.8 14 6.6
Freq > 12MHz (Vcc = 5.5 V)
Icc op max (mA) = 0.9 × Freq (MHz) + 5
Icc Idle max (mA) = 0.3 × Freq (MHz) + 1.7
2.7 V
Max Typ
0.4 0.22
1.5 1.2
2.5 1.7
3 1.9
Idle (1)
3V
Max Typ
0.5 0.24
1.7 1.4
3 2.2
3.8 2.5
3.3 V
Max Typ
0.6 0.27
2 1.6
3.5 2.6
4.5 3
12 MATRA MHS
Rev. E (14 Jan.97)
www.DataSheet.in

12 Page


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