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PDF LMH0394 Data sheet ( Hoja de datos )
| Número de pieza | LMH0394 | |
| Descripción | 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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LMH0394
PRELIMINARY
September 2, 2010
3G HD/SD SDI Low Power Extended Reach Adaptive Cable
Equalizer
General Description
The LMH0394 3 Gbps HD/SD SDI Low Power Extended
Reach Adaptive Cable Equalizer is designed to equalize data
transmitted over cable (or any media with similar dispersive
loss characteristics). The equalizer operates over a wide
range of data rates from 125 Mbps to 2.97 Gbps and supports
SMPTE 424M, SMPTE 292M, SMPTE 344M, SMPTE 259M,
and DVB-ASI standards.
The LMH0394 provides extended cable reach with ultra low
power consumption. The equalizer includes active sensing
circuitry that ensures robust performance and enhanced im-
munity to variations in the input signal launch amplitude. The
output driver offers programmable de-emphasis for up to 40”
of FR4 trace losses. The LMH0394 includes power manage-
ment to further reduce power consumption when no input
signal is present.
The LMH0394 supports two modes of operation. In pin mode,
the LMH0394 operates with control pins to set its operating
state, and is footprint compatible with the LMH0384,
LMH0344, and legacy SDI equalizers. In SPI mode, an op-
tional SPI serial interface can be used to access and configure
multiple LMH0394 devices in a daisy-chain configuration.
This allows programming the output common mode voltage
and swing, output de-emphasis level, input launch amplitude,
and power management settings, as well as access to a cable
length indicator and all pin mode features.
Features
■ SMPTE 424M, SMPTE 292M, SMPTE 344M, SMPTE
259M, and DVB-ASI compliant
■ Equalizes up to 200 meters of Belden 1694A at 2.97 Gbps,
up to 220 meters of Belden 1694A at 1.485 Gbps, or up to
400 meters of Belden 1694A at 270 Mbps
■ Ultra low power consumption: 115 mW (normal operation)
■ Power save mode with auto sleep control (16 mW typical
power consumption in power save mode)
■ Output de-emphasis to compensate for FR4 board trace
losses
■ Digital and analog programmable MUTEREF threshold
control
■ Optional SPI register access
■ Wide range of data rates: 125 Mbps to 2.97 Gbps
■ Internally terminated 100Ω LVDS outputs with
programmable output common mode voltage and swing
■ Programmable launch amplitude optimization
■ Cable length indicator
■ Single 2.5V supply operation
■ 16-pin LLP package
■ Industrial temperature range: −40°C to +85°C
■ Footprint compatible with the LMH0384 and also the
LMH0344, LMH0044, and LMH0074 in pin mode.
Applications
■ SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE
259M serial digital interfaces
■ Broadcast Video routers, switchers, and distribution
amplifiers
Typical Application (Pin Mode)
© 2010 National Semiconductor Corporation 301015
www.DataSheet.in
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FIGURE 3. SPI Read
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FIGURE 6. SPI Daisy Chain System Architecture
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In a daisy-chain configuration of N LMH0394 devices, the host
conceptually sees a shift register of length 16xN. Therefore
the length of SPI transactions (as previously described) is
16xN bits, and SS must be asserted for 16xN clock cycles for
each SPI transaction.
SPI Daisy-Chain Write
Figure 7 shows the SPI daisy-chain write for a daisy-chain of
N devices. The SS signal is driven low and SCK is toggled for
16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in
the daisy-chain) consists of the 16-bit SPI write data for De-
vice N (the last device in the chain), followed by the write data
for Device N-1, Device N-2, etc., ending with the write data
for Device 1 (the first device in the chain). The 16-bit SPI write
data for each device consists of a “0” (write command), seven
address bits, and eight data bits. After the SPI daisy-chain
write, SS must return high and then the write occurs for all
devices in the daisy-chain.
FIGURE 7. SPI Daisy-Chain Write
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SPI Daisy-Chain Read
Figure 8 shows the SPI daisy-chain read for a daisy-chain of
N devices. The SPI daisy-chain read is 32xN bits long, con-
sisting of 16xN bits for the read transaction followed by 16xN
bits for the dummy read transaction (all “1”s) to shift out the
read data on the MISO output. The SS signal is driven low
and SCK is toggled for 16xN clocks. The first 16xN bit MOSI
payload (sent to Device 1 in the daisy-chain) consists of the
16-bit SPI read data for Device N (the last device in the chain),
followed by the read data for Device N-1, Device N-2, etc.,
ending with the read data for Device 1 (the first device in the
chain). The 16-bit SPI read data for each device consists of
a “1” (read command), seven address bits, and eight “1”s
(which are ignored). After the first 16xN bit transaction, SS
must return high (to latch the data) and then is driven low
again before the second 16xN bit transaction of all “1”s is sent
to the MOSI input. The requested read data is shifted out on
MISO starting with the data for Device N and ending with the
data for Device 1. After this transaction, SS must return high.
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LMH0394.PDF ] | |
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