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ISL6265C Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ISL6265C
Beschreibung Multi-Output Controller
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 27 Seiten
ISL6265C Datasheet, Funktion
Multi-Output Controller with Integrated MOSFET
Drivers for AMD SVI Capable Mobile CPUs
ISL6265C
The ISL6265C is a multi-output controller with embedded
gate drivers. A single-phase controller powers the
Northbridge (VDDNB) portion of the CPU. The two
remaining controller channels can be configured for
two-phase or individual single-phase outputs. For
uniplane CPU applications, the ISL6265C is configured as
a two-phase buck converter. This allows the controller to
interleave channels to effectively double the output
voltage ripple frequency, and thereby reduce output
voltage ripple amplitude with fewer components, lower
component cost, reduced power dissipation, and smaller
area. For dual-plane processors, the ISL6265C can be
configured as independent single-phase controllers
powering VDD0 and VDD1.
The heart of the ISL6265C is the patented R3
Technology™, Intersil’s Robust Ripple Regulator
modulator. Compared with the traditional buck regulator,
the R3 Technologyhas a faster transient response. This
is due to the R3 modulator commanding variable
switching frequency during a load transient.
The Serial VID Interface (SVI) allows dynamic
adjustment of the Core and Northbridge output voltages
independently and in combination from 0.500V to 1.55V.
Core and Northbridge output voltages achieve a 0.5%
system accuracy over-temperature.
A unity-gain differential amplifier is provided for remote
CPU die sensing. This allows the voltage on the CPU die
to be accurately regulated per AMD mobile CPU
specifications. Core output current sensing is realized
using lossless inductor DCR sensing. All outputs feature
overcurrent, overvoltage and undervoltage protection.
Features
• Core Configuration Flexibility
- Dual Plane, Single-Phase Controllers
- Uniplane, Two-Phase Controller
• Precision Voltage Regulators
- 0.5% System Accuracy Over-temperature
• Voltage Positioning with Adjustable Load Line and Offset
• Internal Gate Drivers with 2A Driving Capability
• Differential Remote CPU Die Voltage Sensing
• Core Differential Current Sensing: DCR or Resistor
• Northbridge Lossless rDS(ON) Current Sensing
• Serial VID Interface
- Two Wire Clock and Data Bus
- Supports High-Speed I2C
- 0.500V to 1.55V in 12.5mV Steps
- Supports PSI_L Power-Saving Mode
• Core Outputs Feature Phase Shedding with PSI_L
• Adjustable Output-Voltage Offset
• Digital Soft-Start of all Outputs
• User Programmable Switching Frequency
• Static and Dynamic Current Sharing (Uniplane Core)
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free (RoHS compliant)
Applications*(see page 26)
• AMD Griffin Platform CPU
• Notebook Core/GPU Voltage Regulators
Related Literature*(see page 26)
• See FN6884 for “Multi-Output Controller with Integrated
MOSFET Drivers for AMD SVI Capable Mobile CPUs”
Simplified System Diagram
POWER
STAGE
CORE_0
ISL6265C
POWER
STAGE
CORE_1
POWER
STAGE
July 28, 2010
FN6976.1
www.DataSheet.in
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






ISL6265C Datasheet, Funktion
ISL6265C
Simplified Application Circuit for Dual Plane and Northbridge Support
+5V
VIN
SVI DATA
SVI CLOCK
ENABLE
PWROK
VDDPWRGD
REMOTE
SENSE
REMOTE
SENSE
VDD_PLANE_STRAP
VCC PVCC
SVD
SVC
EN
PWROK
PGOOD
VSEN0
RTN0
VSEN1
RTN1
VIN
GND
UGATE0
BOOT0
PHASE0
LGATE0
PGND0
ISP0
ISN0
+VIN
CIN
LOUT
VDD0
CORE
LOAD
OFS/VFIXEN
VDIFF0
RBIAS
OCSET
FB0
COMP0
VW0
VDIFF1
FB1
ISL6265C
UGATE1
BOOT1
PHASE1
LGATE1
PGND1
ISP1
ISN1
COMP1
VW1
FSET_NB
COMP_NB
FB_NB
UGATE_NB
BOOT_NB
PHASE_NB
LGATE_NB
PGND_NB
OCSET_NB
VSEN_NB
RTN_NB
+VIN
CIN
LOUT
VDD1
+VIN
CIN
LOUT
CORE
LOAD
VDDNB
NB
LOAD
FIGURE 2. ISL6265C BASED DUAL-PLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT
SENSING
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ISL6265C pdf, datenblatt
ISL6265C
Electrical Specifications VCC = PVCC = 5V, VIN = 12V, TA = -10°C to +100°C, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -10°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
Overvoltage Threshold
OVHS
VO rising above threshold > 0.5µs
OVERCURRENT PROTECTION VDD0 AND VDD1
1.770 1.800 1.825
V
OCSET Reference Voltage
(VISPx - VISNx)
OVERCURRENT PROTECTION VDD_NB
VOCSET = 180mV; VIN = 15.5V
5 6.0 7 mV
OCSET_NB OCP Current
RBIAS pin to GND = 117kΩ; Trips after
8 PWM cycles
9.2
10 10.8 µA
OFFSET FUNCTION
OFS Pin Voltage For Droop
Enabling
VOFS
ROFS = 240kΩ (OFS pin to GND)
1.18 1.2 1.22
V
FB Pin Source Current
OFS Pin Voltage Threshold for
VFIX Mode and No Droop
Operation
IFB
VOFS
IOFS = =10µA
9.0 9.9 10.8 µA
- 1.8 -
V
OFS Pin Voltage Threshold for
SVI Mode and No Droop
Operation
VOFS
- 4.0 -
V
OFS Bias
LOGIC INPUTS
IOFS
1.8V < OFS < VCC
- 4.0 -
µA
ENABLE Low Threshold
ENABLE High Threshold
ENABLE Leakage Current
VIL(3.3V)
VIH(3.3V)
Logic input is low
-
1.35
0.9
2.0 1.6
-
-1 0
-
V
V
µA
Logic input is high at 3.3V
- 0 1 µA
SVI INTERFACE
PWROK Input Low Threshold
-
0.65
0.8
V
PWROK Input High Threshold
- 0.9 -
V
SVC, SVD Input HIGH (VIH)
1.05
0.87
-
V
SVC, SVD Input LOW (VIL)
-
0.68
0.45
V
Schmitt Trigger Input
Hysteresis
- 0.19 -
V
SVD Low Level Output Voltage
3mA Sink Current
-
0.1 0.285
V
SVC, SVD Leakage
EN = 0V, SVC, SVD = 0V
- < -100 -
nA
EN = 5V, SVC, SVD = 1.8V
- < -100 -
nA
DIFF AMP
Accuracy
VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V
-2
-
2 mV
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested
7. Limits should be considered typical and are not production tested.
8. Limits established by characterization and are not production tested.
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